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參數資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數： | 33/71頁 |
| 文件大小： | 267K |
| 代理商： | TSB12LV01APZ |
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3–15
Example 3–1. Non-Burst Write
80h (ATF_First)
84h (ATF_Continue) DATA2[0:31]
. .
. .
84h (ATF_Continue) DATA(n–1)[0:31]
8Ch (ATF_Continue & Update) DATAn[0:31]
DATA1[0:31]
Example 3–2. Allowable Burst Write
80h (ATF_First)
84h (ATF_Continue) (burst write) DATA2[0:31], DATA3[0:31],
……
, DATA(n–1)[0:31]
8Ch (ATF_Continue & Update) DATAn[0:31]
DATA1[0:31]
Example 3–3. Allowable Burst Write, But Riskier
80h (ATF_First)
8Ch (ATF_Continue & Update) (burst write) DATA2[0:31], DATA3[0:31],
…
., DATA(n–1)[0:31],
DATAn[0:31]
DATA1[0:31]
NOTE:
If writes to ATF_Continued & update do not keep up with data being put on the 1394
bus, an ATF underflow error will occur.
Example 3–4. Allowable Burst Write
A0h (ATF burst write) DATA1[0:31], DATA2[0:31],
…
., DATA(n–1)[0:31], DATAn[0:31]
Example 3–4 only requires one host bus write transaction. The packet is stored in the ATF in the
following format:
{1, DATA1[0:31]}
{0, DATA2[0:31]}
{0, DATA3[0:31]}
.
.
{0, DATA(n–1)[0:31]}
{0, DATAn[0:31]}
3.3.3
The procedure to access to the ITF is as follows:
ITF Access
1.
2.
Write to ITF location 90h: the data is not confirmed for transmission (first quadlet of the packet).
Write to ITF location 94h: the data is not confirmed for transmission (second to n–1 quadlets of the
packet). It is allowed to burst write to ITF_Continue.
Write to ITF location 9Ch: the data is confirmed for transmission (last quadlet of the packet). It is
allowed to burst write to ITF_Continue & Update.
3.
If the first quadlet of a packet is not written to the ITF_First, the transmitter enters a state denoted
by an IFBadF interrupt. An underflow of the ITF also causes an ITFBadF interrupt. When this state
is entered, no isochronous packets can be sent until the ITF is cleared by the CLR ITF control bit.
Asynchronous packets can be sent while in this state.
Example 3–5. ITF Access
The first quadlet of n quadlets is written to ITF location 90h. Quadlets (2 to n–1) are written to ITF
location 94h. The last quadlet (nth) is written to ITF location 9Ch. If the ITFEmpty is true, it is set to
false and the TSB12LV01A requests the phy layer to arbitrate for the bus. To ensure that an ITF
underflow condition does not occur, loading of the ITF in this manner is suggested.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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