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參數(shù)資料
| 型號(hào)： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線(xiàn)鏈路層控制器 |
| 文件頁(yè)數(shù)： | 29/71頁(yè) |
| 文件大小： | 267K |
| 代理商： | TSB12LV01APZ |
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3–11
3.2.10
The ATF status register allows access to the registers that control or monitor the ATF. The register is at
address 30h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is 0000_0000h. This register provides RAM test mode control and status signals.
Asynchronous Transmit-FIFO (ATF) Status Register (@30h)
Table 3–10. ATF Status Register
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
1
2
Full
ATF full flag
When Full is set, the FIFO is full. Write operations are ignored.
Empty
ATF–empty flag
When Empty is set, the FIFO is empty.
ConErr
Control bit error
Each location in the FIFO contains 33-bit data, the MSB is called the
Control bit, which is used to indicate the first quadlet of each packet
for ATF and ITF. In the GRF the control bit is used to indicate whether
the low order 32 bits contain a packet token. If control bit is 1, it indi-
cates that the low order bits at that location are the first quadlet of the
packet in ATF or ITF, or a packet token in GRF. During RAM test
mode, the entire FIFO becomes a RAM. Control bits can be verified
indirectly. If ConErr is1, read value of control bit does not match write
value, which is defined by control (bit 4 of ATF status register). Con-
Err is clear to 0 by writing 1 to AdrClr or 0 to RAM test.
3
AdrClr
Adder clear control
Set AdrClr to 1 to clear AdrCounter and ConErr to 0, during the next
RAM access. The RAM test mode accesses location 0. AdrClr clears
itself to 0.
4
Control
Control bit
The value of control bit is used to relate the MSB of access RAM
location in RAM test mode. For RAM test mode WRITE– control bit
value concatenated with DATA0 – DATA31, writes to the location
pointed by the AdrCounter. For RAM test mode READ– the read
location is pointed to by the current AdrCounter. The read Control
counter bit is compared with Control bit (bit 4) of ATF status register,
if it does not match, it sets ConErr to1.
5
RAMTest
Ram test mode
When RAM test is set to 1, all FIFO function are disabled. Write to or
read from address 80h writes to or reads from the location pointed to
by AdrCounter. After each write or read, AdrCounter is incremented
by 1. AdrCounter address range is from 0 to 511. For normal FIFO
operation , clear RAMTest to 0,and AdrClr, control, AdrCounter are
don’t care.
6–14
15–22
23–31
AdrCounter
Address counter
Gives the address location
Reserved
Reserved
Reserved
ATFSpace-
Count
ATF space count in
quadlets
ATF available space for loading next packet into ATF. If ATFSpace-
Count is larger than the next packet, then the software can burst
write the next packet into ATF. It only requires two host bus transac-
tions: One ATF Status read and one burst write to ATF
This bit or bits are new to the TSB12LV01A and do not exist in the TSB12C01A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:BUS CONTROLLER |
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