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參數資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數： | 62/71頁 |
| 文件大小： | 267K |
| 代理商： | TSB12LV01APZ |
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7–2
7.4.1
Phy Interface Has Control of the Bus
Table 7–1. Phy Interface Control of Bus Functions
CTL0,CTL1
NAME
DESCRIPTION OF ACTIVITY
00
Idle
No activity is occurring (this is the default mode).
01
Status
Status information is being sent from the phy layer to the TSB12LV01A.
10
Receive
An incoming packet is being sent from the phy layer to the TSB12LV01A.
11
Transmit
The TSB12LV01A is given control of the bus to send an outgoing packet.
7.4.2
The TSB12LV01A has control of the bus after receiving permission from the phy layer.
TSB12LV01A Has Control of the Bus
Table 7–2. TSB12LV01A Control of Bus Functions
CTL0, CTL1
NAME
DESCRIPTION OF ACTIVITY
00
Idle
The TSB12LV01A releases the bus (transmission has been completed).
01
Hold
The TSB12LV01A is holding the bus while data is being prepared for transmission, or the
TSB12LV01A wants to send another packet without arbitration.
10
Transmit
An outgoing packet is being sent from the TSB12LV01A to phy layer.
11
Reserved
None
7.5
A serial stream of information is sent across the LREQ terminal whenever the TSB12LV01A needs to
request the bus or access a register that is located in the phy layer. The size of the stream varies depending
on whether the transfer is a bus request, a read command, or a write command. Regardless of the type of
transfer, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end
of the stream.
Request
Table 7–3. Request Functions
NUMBER
of BITS
NAME
7
Bus Request
9
Read Register Request
17
Write Register Request
7.5.1
The definition of the bits in the three different types of transfers is shown in Table 7–4.
LREQ Transfer
7.5.1.1
TSB12LV01A Bus Request
Table 7–4. Bus-Request Functions (Length of Stream: 7 Bits)
BIT(S)
NAME
DESCRIPTION
0
Start bit
Start bit indicates the beginning of the transfer (always set).
1–3
Request type
Request type indicates the type of bus request (see Table 7–7 for the encoding of this
field).
4–5
Request speed
Request speed indicates the speed at which the phy interface sends the packet for this
particular request (see Table 7–8 for the encoding of this field).
6
Stop bit
Stop bit indicates the end of the transfer (always cleared).
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相關代理商/技術參數 |
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| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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