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參數資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學工程師聯合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數： | 101/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV32-EP |
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8
–
8
00
00
10
00
01
XX
dn
d0
SPD
(a)
(e)
(d)
(b)
(c)
FF (
“
data
–
on
”
)
D0
–
D7
CTL0, CTL1
SYSCLK
Figure 8
–
5. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
Receive operation initiated. The Phy indicates a receive operation by asserting receive on the
CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation
may interrupt a status transfer operation that is in progress so that the CTL lines may change from
status to receive without an intervening idle.
Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more
cycles.
Receive operation terminated. The Phy terminates the receive operation by asserting idle on the
CTL lines. The Phy asserts at least one cycle of idle following a receive operation.
Table 8
–
11. Receive Speed Codes
D0
–
D7
DATA RATE
00XX XXXX
S100
0100 XXXX
S200
0101 0000
S400
1YYY YYYY
Data-on indication
NOTE: X = Output as 0 by Phy, ignored by TSB12LV32.
Y = Output as 1 by Phy, ignored by TSB12LV3
8.5
When the TSB12LV32 issues a bus request through the LREQ terminal, the Phy arbitrates to gain control
of the bus. If the Phy wins arbitration for the serial bus, the Phy-LLC interface bus is granted to the
TSB12LV32 by asserting the grant state (
’
b11) on the CTL terminals for one SYSCLK cycle, followed by idle
for one clock cycle. The TSB12LV32 then takes control of the bus by asserting either idle (
’
b00), hold (
’
b01)
or transmit (
’
b10) on the CTL terminals. Unless the TSB12LV32 is immediately releasing the interface, the
TSB12LV32 may assert the idle state for at most one clock before it must assert either hold or transmit on
the CTL terminals. The hold state is used by the TSB12LV32 to retain control of the bus while it prepares
data for transmission. The TSB12LV32 may assert hold for zero or more clock cycles (i.e., the TSB12LV32
need not assert hold before transmit). The Phy asserts data-prefix on the serial bus during this time.
Transmit Operation
When the TSB12LV32 is ready to send data, the TSB12LV32 asserts transmit on the CTL terminals as well
as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until
the last bits of data have been sent. The TSB12LV32 then asserts either hold or idle on the CTL terminals
for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and
placing its CTL and D terminals in high impedance. The Phy then regains control of the interface bus.
The hold state asserted at the end of packet transmission indicates to the Phy that the TSB12LV32 requests
to send another packet (concatenated packet) without releasing the serial bus. The Phy responds to this
concatenation request by waiting the required minimum packet separation time and then asserting grant
as before. This function may be used to send a unified response after sending an acknowledge, or to send
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相關代理商/技術參數 |
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| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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