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參數(shù)資料
| 型號(hào)： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 62/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV32-EP |
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5
–
6
Step 1:
Isochronous header quadlet is loaded into header0 register at 38h through a write
operation from the microcontroller interface.
Step 2:
Header quadlet is forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Isochronous packet is sent to the 1394 bus through the Phy.
NOTE:
The data coming through the data mover port is typically supplied by an external
fast memory block (i.e., FIFO, DRAM). This external memory logic may begin
transmitting data through to the data mover port exactly one DMCLK cycle after the
DMPRE output pin on the GP2Lynx is asserted high.
5.1.2.2
Isochronous Packet Transmit Without Automatic Header Insertion
In this mode, the packet header and data information is loaded through the data mover port. This mode is
sometimes called isochronous packet transmit with manual header insertion. This is because the header
quadlet is not preloaded into the header0 register via the microcontroller interface. Instead, it is inserted
manually
into the data stream at the same time as the rest of the packet. The following steps further illustrate
the process:
Step 1:
Isochronous header information (only one header quadlet in this case) is fetched into the
header0 register at 38h through the data mover port.
Step 2:
Header quadlet is forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Isochronous packet is sent to the 1394 bus through the Phy.
CFR REGISTER
Step 4
Data
Mover
Port
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Step 2
Step 3 (Packet Data)
Packet sent
to 1394 bus
through the
Phy
Step 1 (header fetched)
Step 1
(header supplied)
Step 3
(packet data)
Figure 5
–
8. Isochronous Transmit Without Auto Header Insertion
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PDF描述 |
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| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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