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參數資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學工程師聯合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數： | 54/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV32-EP |
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4
–
1
4 Link Core
This section describes the link core components and operations. Figure 4
–
1 shows the link core
components.
Transmitter
Cycle Timer
Cycle Monitor
CRC
Receiver
P
Figure 4
–
1. Link Core Components
4.1
The physical (Phy) interface provides Phy-level services to the transmitter and receiver. This includes
gaining access to the serial bus, sending packets, receiving packets, and sending and receiving
acknowledge packets. The Phy interface module also interfaces to the Phy chip and implements Texas
Instruments patent-pending bus-holder galvanic isolation.
4.2
Transmitter
The transmitter retrieves data from either the asynchronous transmit FIFO (ATF) or the data mover (DM)
port and creates correctly formatted serial-bus packets to be transmitted through the Phy interface. When
data is present at the ATF interface to the transmitter, the TSB12LV32 Phy interface arbitrates for the serial
bus and sends a packet. When data is present at the DM Port, the TSB12LV32 arbitrates for the serial bus
during the next isochronous cycle. The transmitter autonomously sends the cycle-start packets when the
chip is a cycle master.
4.3
Receiver
The receiver takes incoming data from the Phy interface and determines if the incoming data is addressed
to this node. When the incoming packet is addressed to this node, the CRC of the packet is checked. If the
header CRC is good, the header is confirmed in the general-receive FIFO (GRF). For block and isochronous
packets, the remainder of the packet is confirmed one quadlet at a time. The receiver places a status quadlet
in the GRF after the last quadlet of the packet is confirmed in the GRF. The status quadlet contains the error
code for the packet. In the case of asynchronous packets, the error code is the acknowledge code that is
sent (returned) for that packet. For isochronous and broadcast packets that do not need acknowledge
packets, the error code is the acknowledge code that would have been sent. This acknowledge code tells
the transaction layer whether or not the data CRC is good or bad. If the header CRC is bad, the header is
flushed and the rest of the packet is ignored. When a cycle-start packet is received, it is detected and the
cycle-start packet data is sent to the cycle timer. Cycle-start packets are not placed in the GRF like other
quadlet packets.
Physical Interface
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| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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