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參數資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學工程師聯合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數： | 26/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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2
–
10
BIT
NUMBER
DESCRIPTION
DIR
FUNCTION
BIT NAME
11
LINKON
Link-ON detect
R/W
Set if a link-on pulse is detected on the LINKON input termi-
nal. This bit should be used by software to reactivate the LPS
output to the Phy.
12
ATSTK
Transmitter is
stuck (AT)
R/W
When ATSTK is set, the transmitter has detected invalid data
at the asynchronous transmit-FIFO interface. If the first
quadlet of a packet is not written to the ATF_First or
ATF_First&Update, the underflow of the ATF also causes an
ATStuck interrupt. When this state is entered, no asynchro-
nous packets can be sent until the ATF is cleared by way of
the CLR ATF control bit. Isochronous packets can be sent
while in this state.
13
ATFEMPTY
ATF empty
interrupt
R/W
ATFEMPTY. This bit is set to 1 when the ATF is empty.
14
SNTRJ
Busy
acknowledge
sent by receiver
R/W
When SNTRJ is set, the receiver is forced to send a busy ac-
knowledge to a packet addressed to this node because the
GRF overflowed.
15
HDRERR
Header error
R/W
When HDRERR is set, the receiver detected a header CRC
error on an incoming packet that may have been addressed
to this node.
16
TCERR
Transaction
code error
R/W
When TCERR is set, the transmitter detected an invalid
transaction code in the data at the transmit-FIFO interface.
17
DMACKERR
Data Mover
acknowledge
error
R/W
DM acknowledge error. Set to 1 when the acknowledge re-
ceived is not
ack complete
. When this occurs, DMEN(bit 26)
of the DM Control CFR at04h will be reset to 0 and no more
asynchronous transmit from the DM port will be allowed to
take place until DMEN is set to 1.
18
FIFOACK
FIFO
acknowledge
interrupt
R/W
FIFO ack interrupt. This bit will be set when an acknowledge
from a previous ATF transmit has been received.
19
MCERROR
Micro-interface
error
R/W
Micro-interface error. Set whenever the microcontroller write
protocol is violated.
20
CYSEC
Cycle second
incremented
R/W
When CYSEC is set, the cycle-second field in the cycle timer
register has incremented. This occurs about every second
when the cycle timer is enabled.
21
CYST
Cycle started
R/W
When CYST is set, the transmitter has sent or the receiver
has received a cycle-start packet.
22
CYDNE
Cycle done
R/W
When CYDNE is set, an arbitration gap has been detected
on the bus after the transmission or reception of a cycle-start
packet. This indicates that the isochronous cycle is over.
23
RESERVED
RESERVED
24
CYLST
Cycle lost
R/W
When CYLST is set, the cycle timer has rolled over twice
without the reception of a cycle-start packet. This occurs
only when this node is not the cycle master. All isochronous
traffic stop once CYLST is set. However, asynchronous and
asynchronous streaming traffic will not be affected.
25
CARBFL
Cycle
arbitration failed
R/W
When CARBFL is set, the arbitration to send a cycle-start
packet has failed.
26
ARBGP
Arbitration gap
R/W
When ARBGP is set, the serial bus has been idle for an ar-
bitration reset gap.
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