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參數資料
| 型號： | TSB14AA1T |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電信提供商/數據通信 |
| 文件頁數： | 21/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14AA1T |
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6
–
1
6 Principles of Operation
6.1
PHY/Link Interface Operation
The TSB14AA1A is designed to operate with link layer controllers (LLC) such as the Texas Instruments TSB12LV01B,
TSB12LV21B, and TSB12LV32. Details of operation for the Texas Instruments LLC devices are found in the
respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface.
The interface to the LLC consists of the SCLK, CTL0
–
CTL1, D0
–
D1, LREQ, LPS, and LINKON terminals on the
TSB14AA1A, as shown in Figure 6
–
1.
Link Layer
Controller
SCLK
CTL0
–
CTL1
D0
–
D1
LREQ
LPS
LINKON
TSB14AA1A
Figure 6
–
1. Block Diagram of the TSB14AA1A/LLC Interface
The SCLK terminal provides either a 49.152-MHz interface clock for S100 data transfers or 24.576-MHz interface
clock for S50 data transfers. All control and data signals are synchronized to, and sampled on, the rising edge of
SCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB14AA1A and the LLC.
The D0 and D1 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB14AA1A supports S50 and S100 data transfers over the
D0 and D1 data bus.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to read or write internal PHY registers, or to ask the PHY to initiate a transmit action. The PHY initiates a receive action
whenever a packet is received from the serial bus.
The LPS and LINKON terminals are used for power management of the PHY and LLC. The LPS terminal indicates
the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SCLK. The LINKON
terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC when LPS is inactive.
Note that not all LLCs contain a LINKON terminal, though an external circuit to operate the wake-up mode may always
be implemented at the discretion of the designer.
The TSB14AA1A normally controls the CTL0
–
CTL1 and D0
–
D1 bidirectional busses. The LLC is allowed to drive
these buses only after the LCC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a link service request to read or write a PHY register, or to request the
PHY to gain control of the serial-bus in order to transmit a packet.
The PHY may initiate a status transfer either autonomously or in response to a register request from the LLC.
The PHY initiates a data transmit operation after winning control of the serial-bus following a bus-request by the LLC.
The data transmit operation is initiated when the PHY grants control of the interface to the LLC.
The PHY initiates a data receive operation whenever a packet is received from the serial-bus.
The encoding of the CTL0
–
CTL1 bus is shown in Table 6
–
1 and Table 6
–
2.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14AA1TPFB | 功能描述:IC BACKPLANE PHY 3.3V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| TSB14C01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01AIPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
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