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參數資料
| 型號： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數： | 15/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
SERIAL PERIPHERAL INTERFACE (SPI)
The SPI is a bidirectional serial port. It is used to load the configuration information into the registers listed below as well as to read back
their contents. Table 6 provides a list of the registers that can be programmed through the SPI port. Addresses and default values are given
in hexadecimal form.
Table 6. SPI Address Map
Address (Hex)
Breakdown
Width
Value
Name
POWER CONTROL REGISTERS
0x00
(7:0)
8
0xFF
STBY
Rev. 0 | Page 15 of 44
Bit
Default
Description
Standby control bits (REF, LO, CKO, CK, GC, LNAMX, unused, and
ADC). Default is power-up condition of standby.
CK oscillator bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA,
3 = 0.65 mA).
Do not use.
Factory test mode. Do not use.
0x01
(3:2)
2
0x00
CKOB
0x02
AGC
0x03
0x04
0x05
(1:0)
(7:0)
2
8
0x00
0x00
ADCB
TEST
(7)
(6:0)
(7:0)
(7:4)
1
7
8
4
0
0x00
0x00
0x00
ATTEN
AGCG (14:8)
AGCG (7:0)
AGCA
Apply 16 dB attenuation in the front end.
AGC attenuation setting (7 MSBs of a 15-bit unsigned word).
AGC attenuation setting (8 LSBs of a 15-bit unsigned word).
AGC attack bandwidth setting. Default yields 50 Hz loop
bandwidth.
AGC decay time setting. Default is decay time = attack time.
Enable digital VGA to increase AGC range by 12 dB.
AGC overload update setting. Default is slowest update.
Fast AGC (minimizes resistance seen between GCP and GCN).
AGC enable/reference level (disabled, 3 dB, 6 dB, 9 dB, 12 dB,
15 dB below clip).
0x06
(3:0)
(7)
(6:4)
(3)
(2:0)
4
1
3
1
3
0x00
0
0x00
0
0x00
AGCD
AGCV
AGCO
AGCF
AGCR
DECIMATION FACTOR
0x07
LO SYNTHESIZER
0x08
0x09
(7:5)
(4)
(3:0)
3
1
4
0
0x04
Unused
K
M
Decimation factor = 60 × (
M
+ 1), if
K
= 0; 48 × (
M
+ 1), if
K
= 1.
Default is decimate-by-300.
(5:0)
(7:0)
6
8
0x00
0x38
LOR (13:8)
LOR (7:0)
Reference frequency divider (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default (56) yields 300 kHz from f
REF
= 16.8 MHz.
A Counter (prescaler control counter).
B Counter MSB (5 MSB of a 13-bit word).
Default LOA and LOB values yield 300 kHz from 73.35 MHz to
2.25 MHz.
B Counter LSB (8 LSB of a 13-bit word).
Enable fast acquire.
Invert charge pump (0 = source current to increase VCO
frequency).
Charge pump current in normal operation.
I
PUMP
= (LOI +1) × 0.625 mA.
Manual control of LO charge pump (0 = Off, 1 = Up, 2 = Down,
and 3 = Normal).
LO fast acquire time unit (6 MSBs of a 14-bit word).
LO fast acquire time unit (8 LSBs of a 14-bit word).
0x0A
(7:5)
(4:0)
3
5
0x05
0x00
LOA
LOB (12:8)
0x0B
0x0C
(7:0)
(6)
(5)
8
1
1
0x1D
0
0
LOB (7:0)
LOF
LOINV
(4:2)
3
0x00
LOI
(1:0)
2
0x03
LOTM
0x0D
0x0E
CLOCK SYNTHESIZER
0x10
0x11
(5:0)
(7:0)
6
8
0x00
0x04
LOFA (13:8)
LOFA (7:0)
(5:0)
(7:0)
6
8
0x00
0x38
CKR (13:8)
CKR (7:0)
Reference frequency divisor (6 MSBs of a 14-bit word).
Reference frequency divisor (8 LSBs of a 14-bit word).
Default yields 300 kHz from f
REF
= 16.8 MHz; Minimum = 3,
Maximum = 16383.
Synthesized frequency divisor (5 MSBs of a 13-bit word).
0x12
(4:0)
5
0x00
CKN (12:8)
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