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參數資料
| 型號： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數： | 8/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
PIN 1
TOP VIEW
(Not to Scale)
AD9864
1
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
36
GNDL
35
FREF
34
GNDS
33
SYNCB
32
GNDH
31
FS
30
DOUTB
29
DOUTA
28
CLKOUT
27
VDDH
26
VDDD
25
PE
2
3
4
5
6
7
8
9
10
11
12
48
V
R
13
L
C
42
19
43
L
G
18
44
C
V
17
45
G
G
16
46
C
I
15
47
I
V
14
C
C
41
20
V
G
40
21
39
V
G
22
38
I
P
23
37
G
P
24
0
Figure 2. 48-Lead LFCSP, Backside Paddle Contact Is Connected to Ground
Table 5. Pin Function Descriptions—48-Lead Lead Frame Chip Scale Package (LFCSP)
Pin No.
Mnemonic
Description
1
MXOP
Mixer Output, Positive
2
MXON
Mixer Output, Negative
3
GNDF
Ground for Front End of ADC
4
IF2N
Second IF Input (to ADC), Negative
5
IF2P
Second IF Input (to ADC), Positive
6
VDDF
Positive Supply for Front End of ADC
7
GCP
Filter Capacitor for ADC Full-Scale
Control
8
GCN
Full-Scale Control Ground
9
VDDA
Positive Supply for ADC Back End
10
GNDA
Ground for ADC Back End
11
VREFP
Voltage Reference, Positive
12
VREFN
Voltage Reference, Negative
13
RREF
Reference Resistor: Requires 100 k
to
GNDA
14
VDDQ
Positive Supply for Clock Synthesizer
15
IOUTC
Clock Synth Charge Pump Out Current
16
GNDQ
Ground for Clock Synthesizer Charge
Pump
17
VDDC
Positive Supply for Clock Synthesizer
18
GNDC
Ground for Clock Synthesizer
19
CLKP
Sampling Clock Input/Clock VCO Tank,
Positive
20
CLKN
Sampling Clock Input/Clock VCO Tank,
Negative
21
GNDS
Substrate Ground
22
GNDD
Ground for Digital Functions
23
PC
Clock Input for SPI Port
24
PD
Data I/O for SPI Port
25
PE
Enable Input for SPI Port
26
VDDD
Positive Supply for Internal Digital
Pin No.
27
28
29
30
Mnemonic
VDDH
CLKOUT
DOUTA
DOUTB
Description
Positive Supply for Digital Interface
Clock Output for SSI Port
Data Output for SSI Port
Data Output for SSI Port (Inverted) or
SPI Port
Frame Sync for SSI Port
Ground for Digital Interface
Resets SSI and DecimatorCounters;
Active Low
Substrate Ground
Reference Frequency Input for Both
Synthesizers
Ground for LO Synthesizer
Ground for LO Synthesizer Charge
Pump
LO Synthesizer Charge Pump Out
Current
Positive Supply for LO Synthesizer
Charge Pump
Postive Supply for LO Synthesizer
External Filter Capacitor; DC Output of
LNA
LO Input to Mixer and LO Synthesizer,
Negative
LO Input to Mixer and LO Synthesizer,
Positive
External Bypass Capacitor for LNA
Power Supply
Ground for Mixer and LNA
External Capacitor for Mixer V-I
Converter Bias
First IF Input (to LNA)
Positive Supply for LNA and Mixer
31
32
33
FS
GNDH
SYNCB
34
35
GNDS
FREF
36
37
GNDL
GNDP
38
IOUTL
39
VDDP
40
41
VDDL
CXVM
42
LON
43
LOP
44
CXVL
45
46
GNDI
CXIF
47
48
IFIN
VDDI
Rev. 0 | Page 8 of 44
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