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參數(shù)資料
| 型號(hào)： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁(yè)數(shù)： | 33/44頁(yè) |
| 文件大小： | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
range in the decay time relative to the attack time. The decay
time may be computed from
(
2
/
2
AGCD
)
ATTACK
DECAY
t
t
×
=
(10)
T
V
96
AGCO = 7
TIME (ms)
0.1
0.2
0
0.5
0.4
0.3
80
64
0
48
32
16
1.0
0.9
0.8
0.7
0.6
112
128
AGCO = 4
AGCD = 0
0
Figure 61 shows the AGC response to a 30 Hz pulse-modulated
IF burst for different AGCA and AGCD settings. The 3-bit
value in the AGCO field determines the amount of attenuation
added in response to a reset event in the ADC. Each increment
in AGCO doubles the weighting factor. At the highest AGCO
setting, the attenuation will change from 0 dB to 12 dB in
approximately 10 μs, while at the lowest setting the attenuation
will change from 0 dB to 12 dB in approximately 1.2 ms. Both
times assume
f
CLK
= 18 MHz. Figure 62 shows the AGC attack
time response for different AGCO settings.
Figure 62. AGC Response for Different AGCO Settings with f
CLK
= 18 MSPS,
f
CLKOUT
= 300 kSPS, Decimate by 60 and AGCA = AGCD = 0
AGCA = 0
80
64
0
48
32
16
96
TIME (ms)
10
20
0
50
40
30
80
64
0
48
32
16
96
V
AGCA = 4
80
64
0
48
32
16
96
AGCA = 8
AGCD = 8
AGCD = 0
AGCD = 8
AGCD = 0
AGCD = 8
AGCD = 0
0
Lastly, the AGCF bit reduces the DAC source resistance by at
least a factor of 10. This facilitates fast acquisition by lowering
the RC time constant that is formed with the external capaci-
tors connected from the GCP pin to ground (GCN pin). For an
overshoot-free step response in the AGC loop, the capacitor
connected from the GCP pin to the GCN ground pin should be
chosen so that the RC time constant is less than one quarter of
the raw loop. Specifically
(
)
BW
π
RC
<
8
/
(11)
where
R
is the resistance between the GCP pin and ground
(72.5 k ±30% if AGCF = 0, < 8 k if AGCF = 1) and
BW
is
the raw loop bandwidth. Note that with
C
chosen at this upper
limit, the loop bandwidth increases by approximately 30%.
Now consider the case described above but with the DVGA
enabled to minimize the effects of 16-bit truncation. With the
DVGA enabled, a control loop based on the larger of the two
estimated signal levels, i.e., output of DEC1 and DVGA, is used
to control the DVGA gain. The DVGA multiplies the output of
the decimation filter by a factor of 1 to 4, i.e., 0 dB to 12 dB.
When signals are small, the DVGA gain is 4 and the 16-bit out-
put is extracted from the 24-bit data produced by the decima-
tion filter by dropping 2 MSB and taking the next 16 bits. As
signals get larger, the DVGA gain decreases to the point where
the DVGA gain is 1 and the 16-bit output data is simply the
16 MSB of the internal 24-bit data. As signals get even larger,
attenuation is accomplished by the normal method of increas-
ing the ADC’s full scale.
Figure 61. AGC Response for Different AGCA and AGCD Settings with
f
CLK
= 18 MSPS, f
CLKOUT
= 20 kSPS, Decimate by 900, and AGCO = 0
The extra 12 dB of gain range provided by the DVGA reduces
the input-referred truncation noise by 12 dB and makes the
data more tolerant of LSB corruption within the DSP. The price
paid for this extension to the gain range is that the start of AGC
action is 12 dB lower and that the AGC loop will be unstable if
its bandwidth is set too wide. The latter difficulty results from
the large delay of the decimation filters, DEC2 and DEC3, when
one implements a large decimation factor. As a result, given an
Rev. 0 | Page 33 of 44
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