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參數資料
| 型號： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數： | 37/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
70.5
70.0
–50
–70
–60
–90
–80
71.0
LO FREQUENCY (MHz)
I
0
Figure 68. Expanded View from 70 MHz to 71 MHz
90
50
0
–40
–20
–80
–60
100
IF FREQUENCY (MHz)
d
–120
–100
60
70
80
D =
f
CLK
/4 = 4.5MHz
DESIRED
RESPONSES
0
Figure 69. Response of AD9864 to a –20 dBm IF Input when f
LO
= 71.1 MHz
SPURIOUS RESPONSES
The spectral purity of the LO (including its phase noise) is an
important consideration since LO spurs can mix with unde-
sired signals present at the AD9864’s IFIN input to produce an
in-band response. To demonstrate the low LO spur level intro-
duced within the AD9864, Figure 69 plots the demodulated
output power as a function of the input IF frequency for an LO
frequency of 71.1 MHz and a clock frequency of 18 MHz.
The two large –10 dBFS spikes near the center of the plot are
the desired responses at
f
LO
, ±
f
IF2_ADC
, where
f
IF2_ADC
=
f
CLK
/8, i.e.,
at 68.85 MHz and 73.35 MHz. LO spurs at
f
LO
±
f
SPUR
would
result in spurious responses at offsets of ± f
SPUR
around the
desired responses. Close-in spurs of this kind are not visible on
the plot, but small spurious responses at
f
LO
±
f
IF2_ADC
±
f
CLK
, i.e.,
at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz, are
visible at the –90 dBFS level. This data indicates that the
AD9864 does an excellent job of preserving the purity of the LO
signal.
Figure 69 can also be used to gauge how well the AD9864
rejects undesired signals. For example, the half-IF response (at
69.975 MHz and 72.225 MHz) is approximately –100 dBFS,
giving a selectivity of 90 dB for this spurious response. The
largest spurious response at approximately –70 dBFS occurs
with input frequencies of 70.35 MHz and 71.85 MHz. These
spurs result from third order nonlinearity in the signal path
(i.e.,
abs
[3
× f
LO
–
3
×
f
IF_INPUT
] =
f
CLK
/8).
EXTERNAL PASSIVE COMPONENT REQUIREMENTS
Figure 70 shows an example circuit using the AD9864 and
Table 19 shows the nominal dc bias voltages seen at the differ-
ent pins. The purpose is to show the various external passive
components required by the AD9864, along with nominal dc
voltages for troubleshooting purposes.
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
VREFN
GNDL
FREF
GNDS
SYNCB
GNDH
FS
DOUTB
DOUTA
CLKOUT
VDDH
VDDD
PE
V
I
C
G
C
L
L
C
V
V
I
G
R
13 14 15 16 17 18 19 20 21 22 23 24
V
I
G
V
G
C
C
G
G
P
P
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
25
26
27
28
29
30
31
32
33
34
35
36
AD9864
50
180pF
1
μ
H
1
μ
H
L
100pF
100
pF
2.2nF
100pF
10nF
100pF
100k
10nF
10nF
1
1
1
1
1
1
0
Figure 70. Example Circuit Showing Recommended Component Values
Table 19. Nominal DC Bias Voltages
Pin Number
1
2
4
5
11
12
13
19
20
35
41
42
43
44
46
47
Mnemonic
MXOP
MXON
IF2N
IF2P
VREFP
VREFN
RREF
CLKP
CLKN
FREF
CXVM
LON
LOP
CXVL
CXIF
IFIN
Nominal DC Bias (V)
VDDI – 0.2
VDDI – 0.2
1.3 – 1.7
1.3 – 1.7
VDDA/2 + 0.250
VDDA/2 – 0.250
1.2
VDDC – 1.3
VDDC – 1.3
VDDC/2
1.6 – 2.0
1.65 – 1.9
1.65 – 1.9
VDDI – 0.05
1.6 – 2.0
0.9 – 1.1
Rev. 0 | Page 37 of 44
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