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參數資料
| 型號： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數： | 25/44頁 |
| 文件大小： | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
The 14-bit reference counter and 13-bit N-divider counter can be
programmed via registers
CKR
and
CKN
. The clock frequency,
f
CLK
, is related to the reference frequency by the equation
(
REF
CLK
f
CKR
CKN
f
/
Rev. 0 | Page 25 of 44
×
=
)
(5)
The charge pump current is programmable via the
CKI
register
from 0.625 mA
to 5.0 mA using the equation
(
)
mA
CKI
I
PUMP
625
.
1
×
+
=
(6)
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect func-
tion (enabled by the CKF bit) automatically increases the out-
put current for faster settling during channel changes. The syn-
thesizer may also be disabled using the CK standby bit located
in the STBY register.
2
VDDC = 3.0V
IOUTC
L
OSC
0.1
μ
F
R
BIAS
LOOP
FILTER
R
D
AD9864
CLKN
CLKP
15
19
20
R
F
C
P
C
Z
C
VAR
C
OSC
V
CM
= VDDC – R
BIAS
×
I
BIAS
> 1.6V
f
OSC
> 1/{2
π ×
(L
OSC
×
(C
VARACTOR
||C
OSC
))
1/2
}
CLK OSC. BIAS
I
= 0.15mA, 0.25mA,
0.40mA, OR 0.65mA
0
Figure 40. External Loop Filter, Varactor, and LC Tank
Are Required to Realize a Complete Clock Synthesizer
The AD9864 clock synthesizer circuitry includes a negative
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 40 shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by L
OSC
and the series equivalent
capacitance of C
OSC
and C
VAR
. As a result, L
OSC
, C
OSC
, and C
VAR
should be selected to provide a sufficient tuning range to ensure
proper locking of the clock synthesizer.
The bias, I
BIAS
, of the negative-resistance core has four pro-
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. R
BIAS
should be selected so the
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note that if an external
CLK source or VCO is used, the clock oscillator must be
disabled via the CKO standby bit.
The phase noise performance of the clock synthesizer is
dependent on several factors, including the CLK oscillator I
BIAS
setting, charge pump setting, loop filter component values, and
internal f
REF
setting. Figure 41 and Figure 42 show how the
measured phase noise attributed to the clock synthesizer varies
(relative to an external f
CLK
) as a function of the I
BIAS
setting and
charge pump setting for a –31 dBm IFIN signal at 73.35 MHz
with an external LO signal at 71.1 MHz. Figure 41 shows that
the optimum phase noise is achieved with the highest I
BIAS
(CKO) setting, while Figure 42 shows that the higher charge
pump values provide the optimum performance for the given
loop filter configuration. The AD9864 clock synthesizer and
oscillator were set up to provide an f
CLK
of 18 MHz from an
external f
REF
of 16.8 MHz. The following external component
values were selected for the synthesizer: R
F
= 390 , R
D
= 2 k,
C
Z
= 0.68 μF, C
P
= 0.1 μF, C
OSC
= 91 pF, L
OSC
= 1.2 μH, and C
VAR
= Toshiba 1SV228 Varactor.
–25
–90
–100
–110
–120
d
–20
–15
–10
–5
5
10
15
20
25
FREQUENCY OFFSET (kHz)
–80
–70
–60
–50
–40
–30
–20
–10
–130
–140
CKO = 1
CK0 = 0
CKO = 2
CKO = 3
EXT CLK
0
0
0
Figure 41. CLK Phase Noise vs. I
BIAS
Setting (CKO) (IF = 73.35 MHz,
IF = 71.1 MHz, IFIN = –31 dBm, f
CLK
= 18 MHz, f
REF
= 16.8 MHz)
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with f
REF
= 300 kHz)
–25
–90
–100
–110
–120
d
–20
–15
–10
FREQUENCY OFFSET (kHz)
5
5
10
15
20
25
–80
–70
–60
–50
–40
–30
–20
–10
0
–130
–140
CP = 0
CP = 2
CP = 4
CP = 6
EXT CLK
0
0
Figure 42. CLK Phase Noise vs. I
BIAS
Setting (CKO) (IF = 73.35 MHz,
IF = 71.1 MHz, IFIN = –31 dBm, f
CLK
= 18 MHz, f
REF
= 16.8 MHz) (CLK SYN
Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with f
REF
= 300 kHz
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