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參數資料
| 型號： | AD9864BCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數： | 6/44頁 |
| 文件大?。?/td> | 1984K |
| 代理商： | AD9864BCPZRL |
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AD9864
DIGITAL SPECIFICATIONS
Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
CLK
= 18 MSPS,
f
IF
= 109.65 MHz, f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature
DECIMATOR
Decimation Factor
1
Full
Pass-Band Width
Full
Pass-Band Gain Variation
Full
Alias Attenuation
Full
SPI-READ OPERATION (See Figure 30)
PC Clock Frequency
Full
PC Clock Period (t
CLK
)
Full
PC Clock High (t
HI
)
Full
PC Clock Low (t
LOW
)
Full
PC to PD Setup Time (t
DS
)
Full
PC to PD Hold Time (t
DH
)
Full
PE to PC Setup Time (t
S
)
Full
PC to PE Hold Time (t
H
)
Full
SPI-WRITE OPERATION
2
(See Figure 29)
PC Clock Frequency
Full
PC Clock Period (t
CLK
)
Full
PC Clock High (t
HI
)
Full
PC Clock Low (t
LOW
)
Full
PC to PD Setup Time (t
DS
)
Full
PC to PD Hold Time (t
DH
)
Full
PC to PD (or DOUTB) Data Valid Time (t
DV
)
Full
PE to PD Output Valid to Hi-Z (t
EZ
)
Full
SSI
2
(See Figure 32)
CLKOUT Frequency
Full
CLKOUT Period (t
CLK
)
Full
CLKOUT Duty Cycle (t
HI
, t
LOW
)
Full
CLKOUT to FS Valid Time (t
V
)
Full
CLKOUT to DOUT Data Valid Time (t
DV
)
Full
CMOS LOGIC INPUTS
3
Logic 1 Voltage (V
IH
)
Full
Logic 0 Voltage (V
IL
)
Full
Logic 1 Current (I
IH
)
Full
Logic 0 Current (I
IL
)
Full
Input Capacitance
Full
CMOS LOGIC OUTPUTS
2, 3, 4
Logic 1 Voltage (V
OH
)
Full
Logic 0 Voltage (V
OL
)
Full
Rev. 0 | Page 6 of 44
Test Level
IV
V
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
48
88
100
45
45
2
2
5
5
100
45
45
2
2
3
0.867
38.4
33
–1
–1
VDDH – 0.2
Typ
50%
8
50
10
10
3
VDDH – 0.2
Max
960
1.2
10
10
26
1153
67
+1
+1
0.5
0.2
Unit
f
CLKOUT
dB
dBm
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
V
V
μA
μA
pF
V
V
1
Programmable in steps of 48 or 60.
2
CMOS output mode with C
LOAD
= 10 pF and Drive Strength = 7.
3
Absolute maximum and minimum input/output levels are VDDH + 0.3 V and –0.3 V.
4
I
OL
= 1 mA; specification is also dependent on drive strength setting.
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