欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào)： AD9864BCPZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： IF Digitizing Subsystem
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC48
封裝： LEAD FREE, MO-220VKKD-2, LFCSP-48
文件頁(yè)數(shù)： 4/44頁(yè)
文件大小： 1984K
代理商： AD9864BCPZRL
AD9864
AD9864 SPECIFICATIONS
Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
CLK
= 18 MSPS,
f
IF
= 109.65 MHz, f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature
SYSTEM DYNAMIC PERFORMANCE
1
SSB Noise Figure @ Minimum VGA Attenuation
2, 3
Full
@ Maximum VGA Attenuation
2,3
Full
Dynamic Range with AGC Enabled
2,3
Full
IF Input Clip Point @ Maximum VGA Attenuation
3
Full
@ Minimum VGA Attenuation
3
Full
Input Third Order Intercept (IIP3)
Full
Gain Variation over Temperature
Full
LNA + MIXER
Maximum RF and LO Frequency Range
Full
LNA Input Impedance
25°C
Mixer LO Input Resistance
25°C
LO SYNTHESIZER
LO Input Frequency
Full
LO Input Amplitude
Full
FREF Frequency (for Sinusoidal Input Only)
Full
FREF Input Amplitude
Full
FREF Slew Rate
Full
Minimum Charge Pump Current @ 5 V
4
Full
Maximum Charge Pump Current @ 5 V
4
Full
Charge Pump Output Compliance
5
Full
Synthesizer Resolution
Full
CLOCK SYNTHESIZER
CLK Input Frequency
Full
CLK Input Amplitude
Full
Minimum Charge Pump Output Current
4
Full
Maximum Charge Pump Output Current
4
Full
Charge Pump Output Compliance
5
Full
Synthesizer Resolution
Full
Σ- ADC
Resolution
Full
Clock Frequency (f
CLK
)
Full
Center Frequency
Full
Pass-Band Gain Variation
Full
Alias Attenuation
Full
GAIN CONTROL
Programmable Gain Step
Full
AGC Gain Range
Full
GCP Output Resistance
Full
Rev. 0 | Page 4 of 44
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
VI
VI
VI
IV
IV
IV
VI
VI
VI
VI
IV
IV
V
IV
IV
V
V
IV
Min
91
–20
–32
–12
300
7.75
0.3
8
0.3
7.5
0.4
6.25
13
0.3
0.4
2.2
16
13
80
50
Typ
7.5
13
95
–19
–31
–7.0
0.7
500
370||1.4
1
0.67
5.3
0.67
5.3
f
CLK
/8
16
12
72.5
Max
9.5
2
300
2.0
25
3
VDDP – 0.4
26
VDDC
VDDQ – 0.4
24
26
1.0
95
Unit
dB
dB
dB
dBm
dBm
dBm
dB
MHz
||pF
k
MHz
V p-p
MHz
V p-p
V/μs
mA
mA
V
kHz
MHz
V p-p
mA
mA
V
kHz
Bits
MHz
MHz
dB
dB
dB
dB
k
1
This includes 0.9 dB loss of matching network.
2
AGC with DVGA enabled.
3
Measured in 10 kHz bandwidth.
4
Programmable in 0.67 mA steps.
5
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
相關(guān)PDF資料
PDF描述
AD9866BCPRL Broadband Modem Mixed Signal Front End
AD9866CHIPS Broadband Modem Mixed Signal Front End
AD9866 Broadband Modem Mixed Signal Front End
AD9866-EB Broadband Modem Mixed Signal Front End
AD9866BCP Broadband Modem Mixed Signal Front End
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9864-EB 制造商:Analog Devices 功能描述:
AD9864-EBZ 功能描述:BOARD EVAL FOR AD9864 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:數(shù)字轉(zhuǎn)換器 頻率:10MHz ~ 300MHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AD9864 所含物品:板 標(biāo)準(zhǔn)包裝:1
AD9865 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End
AD9865BCP 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:10BIT MIXED SIGNAL CONVERTER 9865
AD9865BCPRL 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*
主站蜘蛛池模板： 赤水市| 紫云| 呼和浩特市| 柏乡县| 勐海县| 霞浦县| 漳浦县| 安仁县| 唐河县| 平武县| 泗阳县| 鄯善县| 岳阳县| 永丰县| 乌兰浩特市| 开平市| 巴里| 同心县| 连平县| 克拉玛依市| 子洲县| 化州市| 沙坪坝区| 石景山区| 宜都市| 罗甸县| 西昌市| 满洲里市| 会同县| 息烽县| 柳江县| 团风县| 乌兰浩特市| 宿州市| 盐城市| 临漳县| 合水县| 绿春县| 乌兰浩特市| 宜兰县| 泗阳县|