- 您現在的位置：買賣IC網 > PDF目錄374033 > ADSP-21266SKSTZ-2D (ANALOG DEVICES INC) SHARC Embedded Processor PDF資料下載
參數資料
| 型號： | ADSP-21266SKSTZ-2D |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Embedded Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PQFP144 |
| 封裝： | ROHS COMPLIANT, MS-026BFB, LQFP-144 |
| 文件頁數： | 13/44頁 |
| 文件大?。?/td> | 426K |
| 代理商： | ADSP-21266SKSTZ-2D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
ADSP-21266
Rev. B
|
Page 13 of 44
|
May 2005
CLKIN
I
Input only
Local Clock In
. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input.
It configures the ADSP-21266 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21266 to use the external clock source such as
an external clock oscillator. The core is clocked either by the PLL output or this clock
input depending on the CLKCFG1
–
0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.
Crystal Oscillator Terminal
. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control
. These pins set the start up clock frequency. See
Table 6
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
Reset Out/Local Clock Out
. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting Bit 12 of the
PMCTL register. The default is reset out.
Processor Reset
. Resets the ADSP-21266 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
Test Clock (JTAG)
. Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21266.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a
22.5 k
internal pull-up resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a
22.5 k
internal pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21266. TRST has
a 22.5 k
internal pull-up resistor.
Emulation Status
. Must be connected to the ADSP-21266 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a
22.5 k
internal pull-up resistor.
Core Power Supply
. Nominally +1.2 V dc and supplies the DSP’s core processor
(13 pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply
. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the
LQFP package).
Analog Power Supply
. Nominally +1.2 V dc and supplies the DSP’s internal PLL
(clock generator). This pin has the same specifications as V
DDINT
, except that added
filtering circuitry is required.
For more information, see Power Supplies on Page 8.
Analog Power Supply Return
.
Power Supply Return
.
(54 pins on the BGA package, 39 pins on the LQFP package).
XTAL
O
Output only
2
CLKCFG1
–
0
I
Input only
RSTOUT/CLKOUT
O
Output only
RESET
I/A
Input only
TCK
I
Input only
3
TMS
I/S
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
4
Three-state with
pull-up enabled
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
Three-state with
pull-up enabled
V
DDINT
P
V
DDEXT
P
A
VDD
P
A
VSS
GND
G
G
1
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver, with both output path and pull-up disabled.
4
Three-state is a three-state driver, with pull-up disabled.
Table 3. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21363 | SHARC Processor |
| ADSP-21363SBBC-ENG | SHARC Processor |
| ADSP-21363SBBCZENG | SHARC Processor |
| ADSP-21364 | SHARC Processor |
| ADSP-21364SBBC-ENG | SHARC Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21267 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21267SKBCZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21267SKSTZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
| ADSP-21362 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| adsp-21362bbc-1aa | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。