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參數資料
| 型號： | ADSP-21266SKSTZ-2D |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Embedded Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PQFP144 |
| 封裝： | ROHS COMPLIANT, MS-026BFB, LQFP-144 |
| 文件頁數： | 17/44頁 |
| 文件大小： | 426K |
| 代理商： | ADSP-21266SKSTZ-2D |
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ADSP-21266
Rev. B
|
Page 17 of 44
|
May 2005
TIMING SPECIFICATIONS
The ADSP-21266’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1
–
0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21266’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (
Table 8
and
Table 9
).
Figure 5
shows core to CLKIN ratios of 3:1, 8:1, and 16:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2126x SHARC DSP Core Manual
.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See
Figure 30 on Page 37
under Test Conditions for voltage
reference levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Table 8. ADSP-21266 CLKOUT and CCLK Clock
Generation Operation
Timing Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/t
CK
1/t
CCLK
Table 9. Clock Periods
Timing
Requirements
t
CK
t
CCLK
t
SCLK
t
SPICLK
Description
1
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD
register)
DAI_Px = serial port clock
SPICLK = SPI clock
CLKIN Clock Period
(Processor) Core Clock Period
Serial Port Clock Period = (t
CCLK
) × SR
SPI Clock Period = (t
CCLK
) × SPIR
Figure 5. Core Clock and System Clock Relationship to CLKIN
CLKIN
CCLK
(CORE CLOCK)
PLLICLK
XTAL
XTAL
OSC
PLL
3:1, 8:1,
16:1
CLKOUT
CLK-CFG [1:0]
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