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參數資料
| 型號： | ADSP-21266SKSTZ-2D |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | SHARC Embedded Processor |
| 中文描述： | 16-BIT, 66.67 MHz, OTHER DSP, PQFP144 |
| 封裝： | ROHS COMPLIANT, MS-026BFB, LQFP-144 |
| 文件頁數： | 9/44頁 |
| 文件大小： | 426K |
| 代理商： | ADSP-21266SKSTZ-2D |
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ADSP-21266
Rev. B
|
Page 9 of 44
|
May 2005
for the A
VDD
pin. Place the filter components as close as possible
to the A
VDD
/A
VSS
pins. For an example circuit, see
Figure 4
. (A
recommended ferrite chip is the muRata BLM18AG102SN1D).
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
DDINT
and GND. Use wide traces
to connect the bypass capacitors to the analog power (A
VDD
) and
ground (A
VSS
) pins. Note that the A
VDD
and A
VSS
pins specified
in
Figure 4
are inputs to the processor and not the analog
ground plane on the board—the A
VSS
pin should connect
directly to digital ground (GND) at the chip.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The ADSP-21266 is supported by a complete automotive refer-
ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
post processing algorithms that are factory programmed into
the ROM space of the ADSP-21266. SIMD optimized libraries
consume less processing resources, which results in more avail-
able processing power for custom proprietary features.
The nonvolatile memory of the ADSP-21266 can be configured
to contain a combination of Dolby Digital, Dolby Pro Logic,
Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,
and Neo:6. Multiple S/PDIF and analog I/Os are provided to
maximize end system flexibility.
The ADSP-21266 is also supported with a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21266.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21266
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
View mixed C/C++ and assembly code (interleaved source
and object information)
Insert breakpoints
Set conditional breakpoints on registers, memory,
and stacks
Trace instruction execution
Perform linear or statistical profiling of program execution
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
Control how the development tools process inputs and
generate outputs
Maintain a one-to-one correspondence with the tools’
command line switches
Figure 4. Analog Power Filter Circuit
CROSSCORE is a registered trademark of Analog Devices, Inc.
HI Z FERRITE
BEAD CHIP
LOCATE ALL COMPONENTS
CLOSE TO AVDDAND AVSSPINS
AVDD
AVSS
100nF
10nF
1nF
ADSP-212xx
VDDINT
VisualDSP++ is a registered trademark of Analog Devices, Inc.
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| ADSP-21267SKBCZ-X | 制造商:AD 制造商全稱:Analog Devices 功能描述:Preliminary Technical Data |
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