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參數(shù)資料
| 型號： | ISD-SR3000 |
| 文件頁數(shù)： | 19/120頁 |
| 文件大小： | 1293K |
| 代理商： | ISD-SR3000 |
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1-14
1—HARDWARE
ISD-SR3000
Voice Solutions in Silicon
INTERNAL DESCRIPTION
Detailed Description
The Memory Extension unit contains four page registers to perform memory decoding and con-
trol functions, memory mapping and paging.
The page registers are mapped into the I/O Expansion space defined by an active IOCS signal
(*Addresses TBD*)
from the ISD-SR3000. Only address lines A1-A7 are used, while A16 be-
comes DDIN (data direction signal; low for reads). The registers are both writable and readable.
The software accesses the page registers using store or load operations to the respective I/O
ports from the ISD-SR3000. The decoding logic generates the proper signals to write and read
the page registers, which are accessed by the ISD-SR3000 when store and load commands
are executed.
The paging operation works as follows:
When the ISD-SR3000 accesses the expansion memory space (indicated by EMCS going
active), the decoding logic will select one out of the four page registers, based on the state
of A[16:15].
The contents of the selected page register will be use to generate the proper Chip select
and the extended address lines AF[4:0].
Bits 0 to 4 of the page register connect to AF4 to AF0 respectively.
Chip Select field is bits 5 to 7 and are used to generate the Chip Select lines
The chip select signal CFEN will assert low if and only if the value inside the Page register,
which is driving the bus, has a logic 1 at the bit 5 and the signal EMCS is low.
The chip select signals CFRN will assert low if and only if the value inside the Page register,
which is driving the bus, has a logic 1 at bit 6 and the signal EMCS is low.
The chip select signals CFSN will assert low if and only if the value inside the Page register
which is driving the bus has a logic 1 at bit 7 and the signal EMCS is low.
When bits 5, 6, and 7 on the page register are all at logical 0 and the EMCS is asserted low,
the signal CSINROM is asserted low.
Table 1-7: Paging Operation
The mapping of the address from the ISD-SR3000 to the expansion memory is:
Address 0x10000-0x17fff use page register 0.
Address 0x18000-0x1ffff use page register 1.
Address 0x20000-0x27fff use page register 2.
Address 0x28000-0x2ffff use page register 3.
Local Page
Register
7
6
5
4
3
2
1
0
CFSN
CFRN
CFEN
AF[4]
AF[3]
AF[2]
AF[1]
AF[0]
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