
1-24
1—HARDWARE
ISD-SR3000
Voice Solutions in Silicon
1.3.4
In this section, R.E. means Rising Edge and F.E. means Falling Edge.
SYNCHRONOUS TIMING TABLES
Table 1-11: Output Signals
Symbol
Figure
Description
Reference Conditions
Min (ns)
Max (ns)
t
Ah
t
Av
t
CCLKa
t
CCLKh
t
CCLKia
t
CDOh
t
CDOv
t
CTp
Address Hold
After R.E. CTTL
0.0
Address Valid
After R.E. CTTL, T1
9.0
CCLK Active
After R.E. CTTL
12.0
CCLK Hold
After R.E. CTTL
0.0
CCLK Inactive
After R.E. CTTL
12.0
CDOUT Hold
After R.E. CTTL
0.0
-2.0
3
CDOUT Valid
CTTL Clock Period
1
After R.E. CTTL
12.0
R.E. CTTL to next R.E.
CTTL
30.5
250,000
t
EMCSa
t
EMCSh
t
EMCSia
t
FSa
t
FSh
t
FSia
t
MMCLKa
EMCS Active
After R.E. CTTL, T2W1
12.0
EMCS Hold
After R.E. CTTL
0.0
EMCS Inactive
After R.E. CTTL T3
12.0
CFS0 Active
After R.E. CTTL
25.0
CFS0 Hold
After R.E. CTTL
0.0
CFS0 Inactive
After R.E. CTTL
25.0
Master MICROWIRE Clock
Active
After R.E. CTTL
12.0
t
MMCLKh
Master MICROWIRE Clock
Hold
After R.E. CTTL
0.0
t
MMCLKia
Master MICROWIRE Clock
Inactive
After R.E. CTTL
12.0
t
MMDOh
Master MICROWIRE Data Out
Hold
After R.E. CTTL
0.0
t
MMDOv
Master MICROWIRE Data Out
Valid
MICROWIRE Data Float
1
MICROWIRE Data Out Hold
2
MICROWIRE Data No Float
2
MICROWIRE Data Out Valid
2
After R.E. CTTL
12.0
t
MWDOf
t
MWDOh
t
MWDOnf
t
MWDOv
t
MWITOp
t
MWRDYa
After R.E. MWCS
70.0
After F.E. MWCLK
0.0
After F.E. MWCS
0.0
70.0
After F.E. MWCLK
70.0
MWDIN to MWDOUT
Propagation Time
70.0
MWRDY Active
After R.E. of CTTL
0.0
35.0