
1-20
1—HARDWARE
ISD-SR3000
Voice Solutions in Silicon
5.
Guaranteed by design.
6.
I
OUT
= 0, T
A
= 25°C, V
CC
= 3.3 V forV
CC
pins and 3.3 V or5 V on V
CCHI
pins, operating from a 4.096
MHz crystal and running from internal memory with Expansion Memory disabled.
7.
All input signals are tied to 0 (above V
CC
– 0.5 V orbelow V
SS
+ 0.5 V), except ENV0, which is tied to
V
CC
.
8.
Measured in power-down mode. The total current drven, orsourced, by all the ISD-SR3000 processors
output signals is less than 50 μA.
9.
Guaranteed by design, but not fully tested.
10.
CLKIN signal is not 5V tolerant.
t
WRh
WR0 Hold
After R.E. CTTL
t
CTp
/2 –
6
t
WRia
WR0 Inactive
After R.E. CTTL, T3
t
CTp
/
2 + 2
V
ENVh
V
Hh
ENV0 Input, high voltage
CMOS Input with
hysteresis, logical 1 input
voltage
CMOS Input with
hysteresis, logical 0 input
voltage
Hysteresis Loop Width
1
TTL Input, logical 1 input
voltage
2.0
2.1
V
V
V
Hl
0.8
V
V
Hys
V
IH
0.5
2.0
V
V
V
CC
+
0.5
0.8
V
IL
TTL Input, logical 0 input
voltage
Logical 1 TTL, output
voltage
EMCS Logical 1, output
voltage
–0.5
V
V
OH
I
OH
= –0.4 mA
2.4
V
V
OHWC
I
OH
= –50 μA
5
V
CC
–
0.2
V
V
OL
Logical 0, TTL output
voltage
I
OL
= 4 mA
I
OL
= 50 μA
5
I
OL
= 50 μA
5
0.45
0.2
0.2
V
V
V
V
OLWC
EMCS Logical 0, output
voltage
CLKIN Input, high voltage
CLKIN Input, low voltage
V
XH
V
XL
External clock
6
External clock
6
2.0
V
V
0.8
Table 1-10: Electrical Characteristics
(All Parameters with Reference to V
CC
= 3.3V)
Symbol
Parameter
Conditions
Min
Typ
Max
Units