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參數資料
| 型號： | ISD-SR3000 |
| 文件頁數： | 8/120頁 |
| 文件大小： | 1293K |
| 代理商： | ISD-SR3000 |
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1-3
1—HARDWARE
ISD-SR3000
ISD
1.2
DESCRIPTION
This section provides details of the functional characteristics of the ISD-SR3000 processor. It
is divided into the following sections:
Resetting
Clocking
Power-Down Mode
Power and Grounding
Memory Interface
Codec Interface
1.2.1
The RESET pin is used to reset the ISD-SR3000 processor.
RESETTING
On application of power, RESET must be held low for at least t
pwr
after V
CC
is stable. This en-
sures that all on-chip voltages are completely stable before operation. Whenever RESET is ap-
plied, it must also remain active for not less than t
RST
, see Table 1-11 and Table 1-12. During
this period, and for 100 ms after, the TST signal must be high. This can be done with a pull-up
resistor on the TST pins
The value of MWRDY is undefined during the reset period, and for 100 ms after. The microcon-
troller should either wait before polling the signal for the first time, or the signal should be pulled
high during this period.
Upon reset, the ENV0 and ENV1 input pins are sampled to determine the operating environ-
ment. During reset, the EMCS/ENV0 and BMCS/ENV1 pins are used for the ENV0 and ENV1
inputs signals respectively. An internal pull-up resistor sets ENV0 and ENV1 to 1. An external
5.1k
resistor connected to V
ss
can be used to set them to 0.
After reset, the same pin is used for EMCS.
SYSTEM LOAD ON ENV0
For any load on the ENV0 pin, the voltage should not drop below V
ENVh
. Therefore, apply a load
on the ENV0 pin that ensures the voltage does not go below 2.4V.
Figure 1-2 shows a recommended circuit for generating a reset signal when the power is turned
on.
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