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參數資料
型號: ISD-SR3000
文件頁數: 46/120頁
文件大小: 1293K
代理商: ISD-SR3000
2-5
2—SOFTWARE
ISD-SR3000
ISD
Once the recognition engine is initialized, the host controller should wait for the
EV_RECO_QUEUE bit in the status register to be set. When the ISD-SR3000 sets this bit, it
automatically asserts the MWRQST line as an indication for the host controller to read this reg-
ister (by issuing the GSW command). When the host controller has identified this bit, it should
start retrieving the recognized words (noted as topic number and token number) from the ISD-
SR3000 recognition queue buffer using the GNR command. It is the host controller’s responsi-
bility to interpret the incoming words into grammar commands using predefined tables. (These
tables are created by the ISD development tool). When the host controller interprets a valid
command, it can then respond by executing commands such as stopping the recognition en-
gine, playing a prompt or a tone (only after the recognition engine is disabled), changing menus
and topics, adding or deleting user voice tags (a new acoustic word), operating an external de-
vice, etc. The recognition process is half-duplex. When the ISD-SR3000 is playing back audio,
recognition is not active.
Refer to the section Example Operation Procedures on
page 2-68
for examples illustrating
the normal operation procedure for the ISD-SR3000 engine and the adding of a voice tag.
2.5
MICROWIRE/PLUS is a synchronous serial communication protocol that minimizes the num-
ber of connections, and thus the cost, of communicating with peripherals.
HOST CONTROLLER INTERFACE
The ISD-SR3000 MICROWIRE interface implements the MICROWIRE/PLUS interface in slave
mode, with an additional ready signal. It enables a host controller to interface efficiently with the
ISD-SR3000 processor application.
The host controller is the protocol master and provides the clock for the protocol. The ISD-
SR3000 processor supports clock rates of up to 400kHz. This transfer rate refers to the bit
transfer. The actual throughput is slower due to byte processing by the ISD-SR3000 processor
and the host controller.
Communication is handled in bursts of eight bits (one byte). In each burst the ISD-SR3000 pro-
cessor is able to receive and transmit eight bits of data. After eight bits have been transferred,
an internal interrupt is issued for the ISD-SR3000 processor to process the byte, or to prepare
another byte for sending. In parallel, the ISD-SR3000 processor sets MWRDY to 1, to signal
the host controller that it is busy with the byte processing. Another byte can be transferred only
when the MWRDY signal is cleared to 0 by the ISD-SR3000 processor. When the ISD-SR3000
processor transmits data, it expects to receive the value 0xAA before each transmitted byte.
The ISD-SR3000 processor reports any status change by clearing the MWRQST signal to 0.
If processor command’s parameter is larger than one byte, the host controller transmits the
Most Significant Byte (MSB) first. If a return value is larger than one byte, the ISD-SR3000 pro-
cessor transmits the MSB first.
相關PDF資料
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