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參數資料
| 型號： | ISD-SR3000 |
| 文件頁數： | 81/120頁 |
| 文件大小： | 1293K |
| 代理商： | ISD-SR3000 |
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2-40
2—SOFTWARE
ISD-SR3000
Voice Solutions in Silicon
BIT
DESCRIPTION
5
EV_NORMAL_END
0: When this bit is zero, it means either:
a) no command is underway, or
b) a command is being processed but has not yet completed, or
c) a command completed but had an error (as indicated by a ‘1’ in the EV_ERROR
bit)
1: Normal completion of an operation, e.g., end of playing of a prompt.
6
EV_MEMFUL
0: Memory is not full (when using the R command)
1: Memory is full
7
EV_ERROR
0: No error detected
1: Error detected in the last command. The host controller must issue the GEW
command to return the error code and clear the error condition.
10
EV_MEMLOW
0: The ROL memory is not full (when using the RR command)
1: The ROL memory is full (when using the RR command)
11
EV_RECO_QUEUE
0: There are no arguments in the ISD-SR3000 recognition queue.
1: Reco has one or more recognition arguments in its queue.
Use command GNR to retrieve items from the queue.
14
EV_RESET
0: Normally, this bit changes to 0 after performing the INIT command.
1: When the ISD-SR3000 processor completes its power-up sequence and enters
the RESET state, this bit is set to 1, and the MWRQST signal is activated (driven
low).
Normally, this bit changes to 0 after performing the INIT command. If this bit is set
during normal operation of the ISD-SR3000 processor, it indicates an internal ISD-
SR3000 processor error. The host controller can recover from such an error by re-
initializing the system.
15
ERR_RECO
0: No reco error
1: Reco error has occurred. The reco register contains the detailed information.
(Use the GRE command to read the reco error register.)
All other bits
0 or 1: BIts are reserved and should be disregarded. These bits may return any mix
if 0 and1.
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