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| 型號： | ISD-SR3000 |
| 文件頁數(shù)： | 20/120頁 |
| 文件大小： | 1293K |
| 代理商： | ISD-SR3000 |
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1-15
1—HARDWARE
ISD-SR3000
ISD
The signal EMWR is write strobe to external memory. The external SRAM chip can support byte
or word access. In order to support this mode 3 signals are used: LB to support writing to low
byte of the bus, UB to support writing the high byte of the bus, and WR strobe signal. Since the
ISD-SR3000 block can supply WR[0-1] signal for the low or high byte of the bus , the WR strobe
signal needs to be generated, which is the logical AND operation of the two signals. (for more
details, refer to the Winbond W26L010A data sheet).
Note that the block is operational only if the MCFG register of the ISD-SR3000 is programmed
in extension memory mode, 64K x 16 RAM.
The following figures illustrate the timing of Extended Memory Read and Write cycles. Note the
timing of AF[7:5], which result of the qualification of the respective page register outputs with
the delayed EMCS strobe.
Flow Charts
The software on the SR3000 that uses the SR3000 Extended address unit should do the following:
1. Set the MCFG.EMC register to 64kbytes x 16 bits RAM mode. Mode 111 at MCFG.EMC.
2. Set the page register to page xxxxxxxx. For example to the internal ROM use 0x00.
3. To read or write from external memory use load or store operation from the expansion memory. For the
internal ROM the address should be 0x10000 – 0x17fff.
Unit Register Space
The following registers are accessed at addresses <0xFBF2 - 0XFBF*> in the SR3000 I/O ad-
dress space for write operation and addresses <0xFF9e - 0XFFbe> in the SR3000 I/O address
space for read operation.
Table 1-8: Address Mapping from ISD-SR3000 to Expansion Memory
Page Reg #0
Page Reg #1
Page Reg #2
Page Reg #3
A15
0
0
1
1
A16
0
1
0
1
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