
1-25
1—HARDWARE
ISD-SR3000
ISD
1.
2.
3.
In normal operation mode, t
must be 30.5 ns; in power-down mode, t
CTp
must be 50,000 ns.
Guaranteed by design, but not fully tested.
Negative hold times are allowed since they are relative to the internal signal CTTL.
t
MWRDYia
t
PABCh
t
PABCv
MWRDY Inactive
After F.E. MWCLK
0.0
70.0
PB and MWRQST
After R.E. CTTL
0.0
PB and MWRQST
After R.E. CTTL, T2W1
12.0
Table 1-12: Input Signals
Symbol
Figure
Description
Reference Conditions
Min (ns)
Max (ns)
t
CDIh
CDIN Hold
After R.E. CTTL
0.0
t
CDIs
CDIN Setup
Before R.E. CTTL
25.0
t
DIh
Data in Hold (D0:7)
After R.E. CTTL T1, T3 or TI
0.0
t
DIs
Data in Setup (D0:7)
Before R.E. CTTL T1, T3 or
TI
19.0
t
MMDINh
Master MICROWIRE Data
In Hold
After R.E. CTTL
0.0
t
MMDINs
Master MICROWIRE Data
In Setup
Before R.E. CTTL
11.0
t
MWCKh
MICROWIRE Clock High
(slave)
At 2.0 V (both edges)
100.0
t
MWCKl
MICROWIRE Clock Low
(slave)
At 0.8 V (both edges)
100.0
t
MWCKp
MICROWIRE Clock Period
(slave)
1
R.E. MWCLK to next R.E.
MWCLK
2.5 μs
t
MWCLKh
MWCLK Hold
After MWCS becomes
inactive
50.0
t
MWCLKs
MWCLK Setup
Before MWCS becomes
active
100.0
t
MWCSh
MWCS Hold
After F.E. MWCLK
75.0
t
MWCSs
MWCS Setup
Before R.E. MWCLK
100.0
t
MWDIh
MWDIN Hold
After R.E. MWCLK
50.0
t
MWDIs
MWDIN Setup
Before R.E. MWCLK
100.0
Table 1-11: Output Signals
Symbol
Figure
Description
Reference Conditions
Min (ns)
Max (ns)