- 您現在的位置：買賣IC網 > PDF目錄360999 > ISP1761ET (NXP SEMICONDUCTORS) Hi-Speed Universal Serial Bus On-The-Go controller PDF資料下載
參數資料
| 型號： | ISP1761ET |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA128 |
| 封裝： | 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128 |
| 文件頁數： | 21/158頁 |
| 文件大小： | 724K |
| 代理商： | ISP1761ET |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
21 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
7.3.3
PIO mode access—register read cycle
The PIO register read access is similar to a general register access. It is not necessary to
set a prefetching address before a register read.
The ISP1761 register read address will not be automatically incremented during
consecutive read accesses, unlike in a series of ISP1761 memory read cycles. The
ISP1761 register read address must be correctly specified before every access.
7.3.4
PIO mode access—register write cycle
The PIO register write access is similar to a general register access. It is not necessary to
set a prefetching address before a register write.
The ISP1761 register write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The
ISP1761 register write address must be correctly specified before every access.
7.3.5
DMA—read and write operations
The internal ISP1761 Host Controller DMA is a slave DMA. The host system processor or
DMA must ensure the data transfer to or from the ISP1761 memory.
The ISP1761 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit
and 32-bit data bus width. DREQ will be asserted at the beginning of the first burst of a
DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of
that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA
transfer counter was not reached. DREQ will be deasserted on the last cycle when the
DMA transfer counter is reached and will not reasserted until the DMA reprogramming is
performed. Both the DREQ and DACK signals are programmable as active LOW or active
HIGH, according to the system requirements.
The DMA start address must be initialized in the respective register, and the subsequent
transfers will automatically increment the internal ISP1761 memory address. A register or
memory access or access to other system memory can occur in between DMA bursts,
whenever the bus is released because DACK is deasserted, without affecting the DMA
transfer counter or the current address.
Any memory area can be accessed by the system’s DMA at any starting address because
there are no predefined memory blocks. The DMA transfer must start on a word or Double
Word address, depending on whether the data bus width is set to 16-bit or 32-bit. DMA is
the most efficient method to initialize the payload area, to reduce the CPU usage and
overall system loading.
The ISP1761 does not implement EOT to signal the end of a DMA transfer. If
programmed, an interrupt may be generated by the ISP1761 at the end of the DMA
transfer.
The slave DMA of the ISP1761 will issue a DREQ to the DMA controller of the system to
indicate that it is programmed for transfer and data is ready. The system DMA controller
may also start a transfer without the need of the DREQ, if the ISP1761 memory is
available for the data transfer and the ISP1761 DMA programming is completed.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
| ISP2310 | Controller Miscellaneous - Datasheet Reference |
| ISP2312 | Controller Miscellaneous - Datasheet Reference |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1761ET,518 | 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ET,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ET,557 | 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ETGE | 功能描述:IC USB CTRL HI-SPEED 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1761ET-S | 功能描述:IC USB OTG CONTROLLER 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
發布緊急采購，3分鐘左右您將得到回復。