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參數(shù)資料
| 型號(hào)： | ISP1761ET |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA128 |
| 封裝： | 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128 |
| 文件頁(yè)數(shù)： | 26/158頁(yè) |
| 文件大小： | 724K |
| 代理商： | ISP1761ET |
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
26 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
count, the ISP1761 will switch back to suspend mode after the specified time. The
maximum delay that can be programmed in the clock-off count field is approximately
500 ms.
Additionally, the Power Down Control register allows the ISP1761 internal blocks to
disable for lower power consumption as defined in
Table 8
.
The lowest suspend current (I
CC(susp)
) that can be achieved is approximately 150
μ
A at
room temperature. The suspend current will increase with the increase in temperature,
with approximately 300
μ
A at 40
°
C and up to a typical 1 mA at 85
°
C. The system is not in
suspend mode when its temperature increases above 40
°
C. Therefore, even a 1 mA
current consumption by the ISP1761 in suspend mode can be considered negligible. In
normal environmental conditions, when the system is in suspend mode, the maximum
ISP1761 temperature is approximately 40
°
C, determined by the ambient temperature.
Therefore, the ISP1761 maximum suspend current will be below 300
μ
A. An alternative
solution to achieve a very low suspend current is to completely switch off the V
CC(5V0)
power input by using an external PMOS transistor, controlled by one of the GPIO pins of
the processor. This is possible because the ISP1761 can be used in the hybrid mode,
which allows only the V
CC(I/O)
powered on to avoid loading of the system bus.
The time from wake-up to suspend will be approximately 100 ms when the ISP1761
power is always on.
It is necessary to wait for the CLK_RDY interrupt assertion before programming the
ISP1761 because internal clocks are stopped during deep sleep suspend and restarted
after the first wake-up event. The occurrence of the CLK_RDY interrupt means that the
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLK_RDY interrupt will be generated less than 100
μ
s after the
wake-up event, if the power to the ISP1761 was on during suspend.
If the ISP1761 is used in the hybrid mode and V
CC(5V0)
is off during suspend, a 2 ms reset
pulse is required when the power is switched back to on, before starting to program the
resume state. This will ensure that the internal clocks are running and all logics reach a
stable initial state.
7.7 Power supply
Figure 7
shows the ISP1761 power supply connection.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1761ET,518 | 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ET,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ET,557 | 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761ETGE | 功能描述:IC USB CTRL HI-SPEED 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1761ET-S | 功能描述:IC USB OTG CONTROLLER 128TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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