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參數(shù)資料
型號(hào)： MC68HC11A8MCFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 104/158頁
文件大小： 776K
代理商： MC68HC11A8MCFN2
MOTOROLA
10-6
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 1 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Opcode
1B
3A
18 3A
89
99
B9
A9
18 A9
ff
C9
D9
F9
E9
18 E9
ff
8B
9B
BB
AB
18 AB
ff
CB
DB
FB
EB
18 EB
ff
C3
D3
F3
E3
18 E3
ff
84
94
B4
A4
18 A4
ff
C4
D4
F4
E4
18 E4
ff
78
68
18 68
48
58
05
B
C
Cycle
by
Cycle*
Condition Codes
Operand(s)
S X H I N Z V C
- -
¤
-
¤ ¤ ¤ ¤
- - - - - - - -
- - - - - - - -
- -
¤
-
¤ ¤ ¤ ¤
ABA
ABX
ABY
ADCA
(opr)
Add Accumulators
Add B to X
Add B to Y
Add with Carry to A
A + B
→
A
IX + 00:B
→
IX
IY + 00:B
→
IY
A + M + C
→
A
INH
INH
INH
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
IMM
DIR
EXT
IND,X
IND,Y
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
EXT
IND,X
IND,Y
A INH
B INH
INH
1
1
2
2
2
3
2
3
2
2
3
2
3
2
2
3
2
3
2
2
3
2
3
3
2
3
2
3
2
2
3
2
3
2
2
3
2
3
3
2
3
1
1
1
2
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
2
2
3
2-1
2-2
2-4
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
3-3
4-7
5-10
6-10
7-8
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
5-8
6-3
7-3
2-1
2-1
2-2
ii
dd
hh ll
ff
ADCB (opr) Add with Carry to B
B + M + C
→
B
ii
dd
hh ll
ff
- -
¤
-
¤ ¤ ¤ ¤
ADDA (opr) Add Memory to A
A + M
→
A
ii
dd
hh ll
ff
- -
¤
-
¤ ¤ ¤ ¤
ADDB (opr) Add Memory to B
B + M
→
B
ii
dd
hh ll
ff
- -
¤
-
¤ ¤ ¤ ¤
ADDD (opr) Add 16-Bit to D
D + M:M + 1
→
D
jj kk
dd
hh ll
ff
- - - -
¤ ¤ ¤ ¤
ANDA (opr) AND A with Memory
AM
→
A
ii
dd
hh ll
ff
- - - -
¤ ¤
0 -
ANDB (opr) AND B with Memory
BM
→
B
ii
dd
hh ll
ff
- - - -
¤ ¤
0 -
ASL (opr)
Arithmetic Shift Left
hh ll
ff
ff
- - - -
¤ ¤ ¤ ¤
ASLA
ASLB
ASLD
Arithmetic Shift Left Double
- - - -
¤ ¤ ¤ ¤
ASR (opr)
Arithmetic Shift Right
EXT
IND,X
IND,Y
A INH
B INH
REL
DIR
IND,X
IND,Y
REL
REL
REL
REL
REL
REL
77
67
18 67
47
57
24 rr
15
1D
hh ll
ff
ff
3
2
3
1
1
2
3
3
4
2
2
2
2
2
2
6
6
7
2
2
3
6
7
8
3
3
3
3
3
3
5-8
6-3
7-3
2-1
2-1
8-1
4-10
6-13
7-10
8-1
8-1
8-1
8-1
8-1
8-1
- - - -
¤ ¤ ¤ ¤
ASRA
ASRB
BCC (rel)
BCLR (opr)
Branch if Carry Clear
Clear Bit(s)
C = 0
- - - - - - - -
- - - -
¤ ¤
0 -
(msk)
M(mm)
→
M
18 1D
dd mm
ff mm
ff mm
25 rr
27 rr
2C rr
2E rr
22 rr
24 rr
BCS (rel)
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
BHS (rel)
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Branch if Carry Set
Branch if = Zero
Branch if
≥
Zero
Branch if > Zero
Branch if Higher
Branch if Higher or Same
C = 1
Z = 1
N
⊕
V = 0
Z + (N
⊕
V) = 0
C + Z = 0
C = 0
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
C
b0
b7
0
C
b0
b15
0
C
b0
b7
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