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參數資料
| 型號： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 55/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MC68HC11A8
TECHNICAL DATA
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
5-11
5
NF — Noise Flag
The noise flag bit is set if there is noise on any of the received bits, including the start
and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit is cleared
when the SCSR is read (with NF set), followed by a read of the SCDR.
FE — Framing Error
The framing error bit is set when no stop bit was detected in the received data charac-
ter. The FE bit is set at the same time as the RDRF is set. If the byte received causes
both framing and overrun errors, the processor will only recognize the overrun error.
The framing error flag inhibits further transfer of data into the SCDR until it is cleared.
The FE bit is cleared when the SCSR is read (with FE equal to one) followed by a read
of the SCDR.
Bit 0 — Not Implemented
This bit always reads zero.
5.8.5 Baud Rate Register (BAUD)
The baud rate register selects the different baud rates which may be used as the rate
control for the transmitter and receiver. The SCP[0:1] bits function as a prescaler for
the SCR[0:2] bits. Together, these five bits provide multiple baud rate combinations for
a given crystal frequency.
TCLR — Clear Baud Rate Counters (Test)
This bit is used to clear the baud rate counter chain during factory testing. TCLR is
zero and cannot be set while in normal operating modes.
SCP1 and SCP0 — SCI Baud Rate Prescaler Selects
The E clock is divided by the factors shown in
Table 5-1
. This prescaled output pro-
vides an input to a divider which is controlled by the SCR2-SCR0 bits.
SCR2, SCR1, and SCR0 — SCI Baud Rate Selects
These three bits select the baud rates for both the transmitter and the receiver. The
prescaler output described above is further divided by the factors shown in
Table 5-2
.
7
6
0
0
5
4
3
2
1
0
$
1
02B
RESET
TCLR
0
SCP1
0
SCP0
0
RCKB
0
SCR2
U
SCR1
U
SCR0
U
BAUD
Table 5-1 First Prescaler Stage
SCP1
0
0
1
1
SCP0
0
1
0
1
Internal Processor Clock Divided By
1
3
4
13
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