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參數(shù)資料
| 型號(hào)： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 78/158頁 |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MOTOROLA
8-8
PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MC68HC11A8
TECHNICAL DATA
8
PAIF — Pulse Accumulator Input Edge Interrupt Flag
This bit is set when an active edge is detected on the PAI input pin. This bit is cleared
by a write to the TFLG2 register with bit 4 set.
Bits 3-0 — Not Implemented
These bits always read zero.
8.2 Real-Time Interrupt
The real-time interrupt feature on the MCU is configured and controlled by using two
bits (RTR1 and RTR0) in the PACTL register to select one of four interrupt rates. The
RTII bit in the TMSK2 register enables the interrupt capability. Every timeout causes
the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire real time interrupt period elapses before the RTIF flag is set for
the first time.
8.3 Pulse Accumulator
The pulse accumulator is an 8-bit read/write counter which can operate in either of two
modes (external event counting or gated time accumulation) depending on the state
of the PAMOD control bit in the PACTL register. In the event counting mode, the 8-bit
counter is clocked to increasing values by an external pin. The maximum clocking rate
for the external event counting mode is E clock divided by two. In the gated time ac-
cumulation mode, a free-running E clock/64 signal drives the 8-bit counter, but only
while the external PAI input pin is enabled.
The pulse accumulator uses port A bit 7 as its PAI input, but this pin also shares func-
tion as a general purpose l/O pin and as a timer output compare pin. Normally port A
bit 7 would be configured as an input when being used for the pulse accumulator. Note
that even when port A bit 7 is configured for output, this pin still drives the input to the
pulse accumulator.
8.3.1 Pulse Accumulator Control Register (PACTL)
Four bits in this register are used to control an 8-bit pulse accumulator system and two
other bits are used to select the rate for the real time interrupt system.
DDRA7 — Data Direction for Port A Bit 7
0 = Input only
1 = Output
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator off
1 = Pulse accumulator on
7
6
5
4
3
0
0
2
0
0
1
0
$
1
026
RESET
DDRA7
0
PAEN
0
PAMOD
0
PEDGE
0
RTR1
0
RTR0
0
PACTL
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