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參數資料
型號： MC68HC11A8MCFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數： 115/158頁
文件大小： 776K
代理商： MC68HC11A8MCFN2
MC68HC11A8
TECHNICAL DATA
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
10-17
10
4-3
LDD, LDS, LDX
4
1
2
3
4
1
2
Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Opcode Address
Opcode Address + 1
1
1
1
1
1
1
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Register Data (High Byte)
Register Data (Low Byte)
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($DE)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($DF)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Register Data (High Byte)
Register Data (Low Byte)
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode ($9D)
Subroutine Address (Low Byte)
(High Byte Assumed to be $00)
First Subroutine Opcode
Return Address (Low Byte)
Return Address (High Byte)
Opcode (Page Select Byte)
Opcode (Second Byte)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Original Operand Data
Mask Byte
Irrelevant Data
Result Operand Data
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Original Operand Data
Mask Byte
Branch Offset
Irrelevant Data
4-4
STD, STS, STX
4
3
4
1
Operand Address
Operand Address + 1
Opcode Address
0
0
1
4-5
LDY
5
2
3
4
5
1
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Opcode Address
1
1
1
1
1
4-6
STY
5
2
3
4
5
1
2
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Opcode Address
Opcode Address + 1
1
1
0
0
1
1
4-7
ADDD, CPX, SUBD
5
3
4
5
1
2
Operand Address
Operand Address + 1
$FFFF
Opcode Address
Opcode Address + 1
1
1
1
1
1
4-8
JSR
5
3
4
5
1
2
3
Subroutine Address
Stack Pointer
Stack Pointer – 1
Opcode Address
Opcode Address + 1
Opcode Address + 2
1
0
0
1
1
1
4-9
CPD, CPY
6
4
5
6
1
2
Operand Address
Operand Address + 1
$FFFF
Opcode Address
Opcode Address + 1
1
1
1
1
1
4-10
BCLR, BSET
6
3
4
5
6
1
2
Operand Address
Opcode Address + 2
$FFFF
Operand Address
Opcode Address
Opcode Address + 1
1
1
1
0
1
1
4-11
BRCLR, BRSET
6
3
4
5
6
Operand Address
Opcode Address + 2
Opcode Address + 3
$FFFF
1
1
1
1
Table 10-4 Cycle-by-Cycle Operation — Direct Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-refrerence to Table 10-1.
相關PDF資料
PDF描述
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參數描述
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