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參數(shù)資料
| 型號(hào)： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 40/158頁 |
| 文件大?。?/td> | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MOTOROLA
4-2
PARALLEL I/O
MC68HC11A8
TECHNICAL DATA
4
4.3 Simple Strobed I/O
The simple strobed mode of parallel l/O is invoked and controlled by the parallel l/O
control register (PIOC). This mode is selected when the handshake bit (HNDS) in the
PIOC register is clear. Port C becomes a strobed input port with the STRA line as the
edge-detecting latch command input. Also, port B becomes a strobed output port with
the STRB line as the output strobe. The logic sense of the STRB output is selected by
the invert strobe B bit (INVB) in the PIOC register.
4.3.1 Strobed Input Port C
In this mode, there are two addresses where port C may be read, the PORTC data
register and the alternate latched port C register (PORTCL). The data direction regis-
ter still controls the data direction of all port C lines. Even when the strobed input mode
is selected, any or all of the port C lines may still be used for general purpose l/O.
The STRA line is used as an edge-detecting input, and the edge-select for strobe A
(EGA) bit in the PIOC register defines either falling or rising edge as the significant
edge. Whenever the selected edge is detected at the STRA pin, the current logic levels
at port C lines are latched into the PORTCL register and the strobe A flag (STAF) in
the PIOC register is set. If the strobe A interrupt enable (STAI) bit in PIOC is also set,
an internal interrupt sequence is requested. The strobe A flag (STAF) is automatically
cleared by reading the PIOC register (with STAF set) followed by a read of the
PORTCL register. Data is latched in the PORTCL register whether or not the STAF
flag was previously clear.
4.3.2 Strobed Output Port B
In this mode, the STRB pin is a strobe output which is pulsed for two E clock periods
each time there is a write to port B. The INVB bit in the PIOC register controls the po-
larity of the pulse on the STRB line.
4.4 Full Handshake I/O
The full handshake modes of parallel l/O involve port C and the STRA and STRB lines.
There are two basic modes (input and output) and an additional variation on the output
handshake mode that allows three-stated operation of port C. In all handshake modes,
STRA is an edge-detecting input, and STRB is a handshake output line.
When full input handshake protocol is specified, both general purpose input and/or
general purpose output can coexist at port C. When full output handshake protocol is
specified, general purpose output can coexist with the handshake outputs at port C,
but the three-state feature of the output handshake mode interferes with general pur-
pose input in two ways. First, in full output handshake, the port C lines are outputs
whenever STRA is at its active level regardless of the data direction register bits. This
potentially conflicts with any external device trying to drive port C unless that external
device has an open-drain type output driver. Second, the value returned on reads of
port C is the state of the outputs of an internal port C output latch regardless of the
states of the data direction register bits, so that the data written for output handshake
can be read even if the pins are in a three-state condition.
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