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參數資料
| 型號： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 60/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MOTOROLA
6-2
SERIAL PERIPHERAL INTERFACE
MC68HC11A8
TECHNICAL DATA
6
6.2.3 Serial Clock (SCK)
The serial clock is used to synchronize data movement both in and out of the device
through its MOSI and MISO lines. The master and slave devices are capable of ex-
changing a byte of information during a sequence of eight clock cycles. Since SCK is
generated by the master device, this line becomes an input on a slave device.
As shown in
Figure 6-1
, four possible timing relationships may be chosen by using
control bits CPOL and CPHA in the serial peripheral control register (SPCR). Both
master and slave devices must operate with the same timing. The master device al-
ways places data on the MOSI line a half-cycle before the clock edge (SCK), in order
for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In
a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
6.2.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to be low prior
to data transactions and must stay low for the duration of the transaction.
The SS line on the master must be tied high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). The SS pin can be se-
lected to be a general-purpose output by writing a one in bit 5 of the port D data direc-
tion register, thus disabling the mode fault circuit. The other three SPI lines are
dedicated to the SPI whenever the SPI is on.
Figure 6-1 Data Clock Timing Diagram
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode,
SS must go high between successive characters in an SPI message. When CPHA =
1, SS may be left low for several SPI characters. In cases where there is only one SPI
slave MCU, its SS line could be tied to V
SS
as long as CPHA = 1 clock modes are used.
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
(CPHA = 0) DATA OUT
(CPHA = 1) DATA OUT
SS (TO SLAVE)
SAMPLE INPUT
SAMPLE INPUT
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
SPI TRANSFER FORMAT
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