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參數資料
| 型號： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 85/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MC68HC11A8
TECHNICAL DATA
RESETS, INTERRUPTS, AND LOW POWER MODES
MOTOROLA
9-5
9
of reset. The DLY control bit is set to specify that an oscillator start-up delay is imposed
upon recovery from STOP mode. The clock monitor system is disabled by CME equal
zero.
9.1.3 Computer Operating Properly (COP) Reset
The MCU includes a computer operating properly watchdog system to help protect
against software failures. To use a COP watchdog timer, a watchdog timer reset se-
quence must be executed on a regular periodic basis so that the watchdog timer is
never allowed to time out.
The internal COP function includes special control bits which permit specification of
one of four time out periods and even allows the function to be disabled completely.
The COP system has a separate reset vector.
The NOCOP control bit, which determines whether or not a watchdog timeout causes
a system reset, is implemented in an EEPROM cell in the CONFIG register. Once pro-
grammed, this bit remains set (or cleared) even when no power is applied, and the
COP function is enabled or disabled independent of resident software. The NOCOP
control bit may be preempted while in special modes to prevent the COP system from
causing a hardware reset.
Two other control bits in the OPTION register select one of four timeout durations for
the COP timer. The actual timeout period is dependent on the system E clock frequen-
cy, but for reference purposes,
Table 9-1
shows the relationship between the CR1 and
CR0 control bits and the COP timeout period for various system clock frequencies.
The default reset condition of the CR1 and CR0 bits is cleared which corresponds to
the shortest timeout period.
The sequence required to reset the watchdog timer is:
1. Write $55 to the COP reset register (COPRST) at $103A, followed by
2. Write $AA to the same address.
Both writes must occur in correct order prior to timeout but, any number of instructions
may be executed between the writes. The elapsed time between adjacent software re-
set sequences must never be greater than the COP time out period. Reading the CO-
PRST register does not return meaningful data and does not affect the watchdog
timer.
Table 9-1 COP Timeout Period versus CR1 and CR0
CR1 CR0
Rate
XTAL = 12.0
MHz Timeout
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
XTAL = 2
23
Timeout
– 0/+15.6 ms
15.625 ms
62.5 ms
250 ms
1 s
2.1 MHz
XTAL = 8.0 MHz
Timeout
– 0/+16.4 ms
16.384 ms
65.536 ms
262.14 ms
1.049 s
2.0 MHz
XTAL = 4.9152
MHz Timeout
– 0/+26.7 ms
XTAL = 4.0 MHz
Timeout
– 0/+32.8 ms
32.768 ms
131.07 ms
524.29 ms
2.1 s
1.0 MHz
XTAL = 3.6864
MHz Timeout
– 0/+35.6 ms
0
0
1
1
0
1
0
1
2
15
÷
E
2
17
÷
E
2
19
÷
E
2
21
÷
E
E =
26.667 ms
106.67 ms
426.67 ms
1.707 s
1.2288 MHz
35.556 ms
142.22 ms
568.89 ms
2.276 s
921.6 kHz
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