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參數資料
| 型號： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 54/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MOTOROLA
5-10
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
TECHNICAL DATA
5
5.8.4 Serial Communications Status Register (SCSR)
The serial communications status register (SCSR) provides inputs to the interrupt logic
circuits for generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty
The transmit data register empty bit is set to indicate that the content of the serial com-
munications data register have been transferred to the transmit serial shift register.
This bit is cleared by reading the SCSR (with TDRE = 1) followed by a write to the
SCDR.
TC — Transmit Complete
The transmit complete bit is set at the end of a data frame, preamble, or break condi-
tion if:
1. TE = 1, TDRE = 1, and no pending data, preamble, or break is to be transmitted;
or
2. TE = 0, and the data, preamble, or break in the transmit shift register has been
transmitted.
The TC bit is a status flag which indicates that one of the above conditions have oc-
curred.
The TC bit is cleared by reading the SCSR (with TC set) followed by a write to the
SCDR.
RDRF — Receive Data Register Full
The receive data register full bit s set when the receiver serial shift register s transferred to
the SCDR. The RDRF bit is cleared when the SCSR is read (with RDRF set) followed by a
read of the SCDR.
IDLE — Idle Line Detect
The dle ine detect bit, when set, ndicates the receiver has detected an dle ine. The IDLE
bit s cleared by reading the SCSR with IDLE set followed by reading SCDR. Once the IDLE
status flag is cleared, it will not be set again until after the RxD line has been active and be-
comes idle again.
OR — Overrun Error
The overrun error bit s set when he next byte s ready o be ransferred rom he receive shift
register to the SCDR which is already full (RDRF bit is set). When an overrun error occurs,
the data which caused he overrun s ost and he data which was already n SCDR s not dis-
turbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the
SCDR.
7
6
5
4
3
2
1
0
0
0
$
1
02E
RESET
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
SCSR
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