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參數資料
| 型號： | MC68HC11A8MCFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 47/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8MCFN2 |
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MC68HC11A8
TECHNICAL DATA
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
5-3
5
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sam-
pled three times at RT intervals 8 RT, 9 RT, and 10 RT (1 RT is the position where the
bit is expected to start), as shown in
Figure 5-2
. The value of the bit is determined by
voting logic which takes the value of the majority of samples.
Figure 5-2 Sampling Technique Used on All Bits
5.5 Start Bit Detection
When the RxD input is detected low, it is tested for three more sample times (referred
to as the start edge verification samples in
Figure 5-3
). If at least two of these three
verification samples detect a logic zero, a valid start bit has been detected, otherwise
the line is assumed to be idle. A noise flag is set if all three verification samples do not
detect a logic zero. A valid start bit could be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8-bit format
or 11 zeros for 9-bit format), the circuit continues to operate as if there actually was a
stop bit and the start edge will be placed artificially. The last bit received in the data
shift register is inverted to a logic one, and the three logic one start qualifiers (shown
in
Figure 5-3
) are forced into the sample shift register during the interval when detec-
tion of a start bit is anticipated (see
Figure 5-4
); therefore, the start bit will be accepted
no sooner than it is anticipated.
If the receiver detects that a break produced the framing error, the start bit will not be
artificially induced and the receiver must actually detect a logic one before the start bit
can be recognized. See
Figure 5-5
.
16
R
T
1
R
T
8
R
T
9
R
T
10
R
T
RxD
SCI BIT SAMPLING
PREVIOUS BIT
PRESENT BIT
SAMPLES
NEXT BIT
16
R
T
1
R
T
v
v
v
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