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參數資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 63/80頁 |
| 文件大小： | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
63
Table 92. REGISTER 0x7C Configuration Register 5 (PowerOn Default = 0x05)
Bit
Description
R/W
(Note 38)
Name
<4>
PECI
T
CONTROL
R/W
PECI = 1 enables THERM
assertions when the PECI temperature read is higher than the PECI
T
CONTROL
limit and the THERM
pin is bidirectional. If THERM
is configured as an output the
THERM
timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being
generated.
PECI = 0 indicates that the THERM
pin is configured as a timer input only. Can also be disabled
by writing 128癈 to the relevant PECI T
CONTROL
limit register.
<5>
R1 THERM
R/W
R1 = 1 enables THERM
assertions when the Remote 1 temperature read is higher than the
Remote 1 THERM
limit and the THERM
pin is bidirectional. If THERM
is configured as an out-
put the THERM
timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from
being generated.
R1 = 0 indicatesthat the THERM
pin is configured as a timer input only.
can also be disabled by writing one of the below values to the Remote 1 THERM
limit register
(0x6A): Writing 64癈 in offset 64 mode.
Writing 128癈 in twos complement mode.
<6>
Local
THERM
R/W
Local = 1 enables THERM
assertions when the Local temperature read is higher than the Local
THERM
limit and the THERM
pin is bidirectional. If THERM
is configured as an output the
THERM
timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from being
generated.
can also be disabled by writing one of the below values to the Remote 1 THERM
limit register
(0x6B): Writing 64癈 in offset 64 mode.
Writing 128癈 in twos complement mode.
<7>
R2 THERM
R/W
R2 = 1 enables THERM
assertions when the Remote 2 temperature read is higher than the
Remote 2 THERM
limit and the THERM
pin is bidirectional. If THERM
is configured as an out-
put the THERM
timer limit (register 0x7A) should be set to 0xFF to avoid unwanted alerts from
being generated.
can also be disabled by writing one of the below values to the Remote 1 THERM
limit register
(0x6C): Writing 64癈 in offset 64 mode.
Writing 128癈 in twos complement mode.
38.This register becomes readonly when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have
no effect.
Table 93. REGISTER 0x7D Configuration Register 4 (PowerOn Default = 0x00)
Bit
Name
R/W
(Note 39)
Description
<1:0>
PIN14FUNC
R/W
These bits set the functionality of Pin 14:
00 = TACH4 (default)
01 = THERM
10 = SMBALERT
11 = RESERVED
Note: Pin 14 refers to the QSOP package. The equivalent pin on the QFN package is pin 11.
<2>
THERM
Disable
R/W
THERM
Disable = 0 enables THERM
overtemperature output assuming THERM
is correctly
configured (registers 0x78, 0x7C, 0x7D).
THERM
Disable = 1 disables THERM
overtemperature output on all channels.
THERM
can also be disabled on any channel by:
Writing 64癈 to the appropriate THERM
temperature limit in offset 64 mode.
Writing 128癈 to the appropriate THERM
temperature limit in twos complement mode.
<3>
BpAtt Vtt
R/W
Bypass Vtt attenuator. When set, the measurement scale for this channel changes from 0 V
(0x00) to 2 V (0xFF).
<4>
BpAtt2.5 V
R/W
Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V
(0x00) to 2 V (0xFF).
<5>
BpAttV
CCP
R/W
Bypass V
CCP
attenuator. When set, the measurement scale for this channel changes from 0 V
(0x00) to 2 V (0xFF).
<6>
BpAtt5 V
R/W
Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V
(0x00) to 2 V (0xFF).
<7>
BpAtt12 V
R/W
Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V
(0x00) to 2 V (0xFF).
39.This register becomes readonly when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no
effect.
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