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參數資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 64/80頁 |
| 文件大小： | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
64
Table 94. REGISTER 0x7E Interrupt Status 5 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
PUSH0
R
Logic 1 indicates ALERT assertion for Push0 temperature
<1>
PUSH1
R
Logic 1 indicates ALERT assertion for Push1 temperature
<2>
PUSH2
R
Logic 1 indicates ALERT assertion for Push2 temperature
<3>
PUSH3
R
Logic 1 indicates ALERT assertion for Push3 temperature
<4>
OVT_P0
R
Logic 1 indicates THERM assertion for Push0 temperature
<5>
OVT_P1
R
Logic 1 indicates THERM assertion for Push1 temperature
<6>
OVT_P2
R
Logic 1 indicates THERM assertion for Push2 temperature
<7>
OVT_P3
R
Logic 1 indicates THERM assertion for Push3 temperature
Table 95. REGISTER 0x7F Interrupt Mask 5 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
PUSH0
R/W
Logic 1 masks PUSH0 ALERT assertions
<1>
PUSH1
R/W
Logic 1 masks PUSH1 ALERT assertions
<2>
PUSH2
R/W
Logic 1 masks PUSH2 ALERT assertions
<3>
PUSH3
R/W
Logic 1 masks PUSH3 ALERT assertions
<4>
Reserved
R
Reserved
<5>
Reserved
R
Reserved
<6>
Reserved
R
Reserved
<7>
Reserved
R
Reserved
Table 96. REGISTER 0x80 GPIO Register (PowerOn Default = 0xCE )
Bit
Name
R/W
Description
<0>
RES
RESERVED
<1>
GPEN
1= GPIO1 enabled on pin 5, GPIO2 enabled on pin 6
0 = GPIO1 and GPIO2 are disabled
This bit only has effect if the SMBus master port is disabled (0xB5 <0> =0)
<2>
GPIO2
R/W
If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as
an output, writing to this register asserts the output high or low depending on the polarity.
<3>
GPIO1
R/W
If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as
an output, writing to this register asserts the output high or low depending on the polarity.
<4>
GPIO2 POL
R/W
GPIO2 polarity bit. Set to 0 for active low. Set to1 for active high.
<5>
GPIO1 POL
R/W
GPIO1 polarity bit. Set to 0 for active low. Set to1 for active high.
<6>
GPIO2 DIR
R/W
GPIO2 direction bit. Set to 1 for GPIO2 to act as an input, set to 0 for GPIO2 to act as an
output.
<7>
GPIO1 DIR
R/W
GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an
output.
Table 97. REGISTER 0x81 Interrupt Status Register 4 (PowerOn Default = 0x00)
Bit
Name
R/W
Description
<0>
PCC
R
PECI Completion code interrupt
<1>
TTS
R
Logic 1 indicates that the THERM Timer limit has been exceeded.
<2>
GCOMM
R
Logic 1 indicates a COMM error resulting from a Generic PECI instruction
<3>
PECI1
R
A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI1 value.
<4>
PECI2
R
A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI2 value.
<5>
PECI3
R
A logic 1 indicates that the PECI high or low limit has been exceeded by the PECI3 value.
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