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參數資料
| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數： | 102/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01B-EP |
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8
–
9
consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is
enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed
of the packet is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of
Phy register 5 is set), the TSB12LV32 must specify the speed code of the next concatenated packet on the
D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed
code is the same as the speed code that precedes received packet data as given in Table 8
–
11.
After sending the last packet for the current bus ownership, the TSB12LV32 releases the bus by asserting
Idle on the CTL terminals for two clock cycles. The Phy begins asserting Idle on the CTL terminals one clock
after sampling Idle from the link. Note that whenever the D and CTL terminals change direction between
the Phy and the TSB12LV32, there is an extra clock period allowed so that both sides of the interface can
operate on registered versions of the interface signals.
00
00
00
00
01
00
(f)
SPD
00
10
(g)
(e)
(d)
(c)
(b)
(a)
01
00
00
00
00
00
11
dn
d0
Link controls CTL and D
Phy CTL and D outputs are High Impedance
D0
–
D7
CTL0, CTL1
SYSCLK
NOTE: SPD = Speed code, see Table 8
–
11, d0
–
dn = Packet data
Figure 8
–
6. Normal Packet Transmission Timing
The sequence of events for a normal packet transmission is as follows:
Transmit operation initiated. The Phy asserts grant on the CTL lines followed by Idle to hand over
control of the interface to the link so that the link may transmit a packet. The Phy releases control
of the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle
cycle.
Optional idle cycle. The link may assert at most one Idle cycle preceding assertion of either hold
or transmit. This idle cycle is optional; the link is not required to assert Idle preceding either hold
or transmit.
Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit.
These hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
相關PDF資料 |
PDF描述 |
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| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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