- 您現在的位置：買賣IC網 > PDF目錄365967 > TSB12LV01B-EP FPGA (Field-Programmable Gate Array) PDF資料下載
參數資料
| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數： | 51/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01B-EP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
3
–
14
BCLK
MWR
MCS
MCA
MA[0:6]
MD[0:15]
TEA
M8BIT/
SIZ0
MCMODE/
SIZ1
XX
XX
XX
XXXX
XXXX
XXXX
S0
S1
D0
S2
H0
H1
H2
S3
S4
H3
H4
D2
D1
S5
H5
ADDRESS
DATA
ADDRESS
DATA
3.3.5
The term
endianness
refers to the way data is referenced and stored in a processor
’
s memory. For example,
consider a 32-bit processor; any 32-word consists of four bytes which may be stored in memory in one of
two ways. Of the four bytes, either byte 3 will be considered the most significant byte and byte 0 the least
significant byte, or vice versa (see Figures 3
–
15 and 3
–
16). A little endian type memory considers byte 0
the least significant byte, whereas a big endian type memory considers byte 3 to be the least significant byte.
Endian Swapping
Byte #0
(Most Significant Byte)
Byte #1
Byte #2
Byte #3
(Least Significant Byte)
Figure 3
–
15. Big Endian Format
Byte #3
(Most Significant Byte)
Byte #2
Byte #1
Byte #0
(Least Significant Byte)
Figure 3
–
16. Little Endian Format
The TSB12LV32 configuration register space (CFR) and FIFO memory, both of which are 32-bits wide, use
a big endian architecture. The TSB12LV32 uses the same endianness as the internal P1394 link core. This
means that the most significant byte is the left-most byte (byte 0) and the least significant byte is the right
most byte (byte 3).
3.3.5.1
For little-endian processors, there are two modes of byte swapping, address invariant and data invariant.
Address invariance preserves byte ordering between the internal system (GP2Lynx registers and FIFO) and
external system (microcontroller/processor). Data invariance preserves the bit significance of the data, but
changes the byte significance between the internal and external systems. The MDINV pin controls how the
write/read data is swapped at the data bus (i.e., determines how the received bytes from the microcontroller
are mapped into the TSB12LV32 internal registers and memory space). Note that when the COLDFIRE pin
is high, the MDINV pin has no affect and data is always interpreted in as big endian. Refer to Literature
Data and Address Invariance for Little Endian Processors
相關PDF資料 |
PDF描述 |
|---|---|
| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發布緊急采購，3分鐘左右您將得到回復。