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參數(shù)資料
| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強(qiáng)塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數(shù)： | 28/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01B-EP |
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2
–
12
2.2.6
Isochronous Port Register at 18h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
T
T
M
IRPORT1
IRPORT2
ISYNCRCVN
I
The power-up reset value of this register = 0000_0000h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
–
1
TAG1
Tag Field 1
R/W
The TAG1 field can further qualify the isochronous reception
for isochronous Receive PORT1 when the MONTAG bit is set.
2
–
7
IRPORT1
Isochronous
receive port
1 channel
number
R/W
IR port1 contains the channel number of the isochronous
packets that the receiver accepts. The receiver accepts
isochronous packets with this channel number when the
IRP1EN is set.
8
–
9
TAG2
Tag Field 2
R/W
The TAG2 field can further qualify the isochronous reception
for isochronous Receive PORT2 when the MONTAG bit is set.
10
–
15
IRPORT2
Isochronous
receive port
2 channel
number
R/W
IR port2 contains the channel number of the isochronous
packets that the receiver accepts. The receiver accepts
isochronous packets with this channel number when the
IRP2EN is set.
16
–
23
RESERVED
Reserved
24
–
27
ISYNCRCVN
Synchronous
Enable
R/W
In isochronous receive mode to the DM port, when the
ISYNCRCVN enable bits are high, the DMPRE terminal pulses
when an isochronous packet is received whose SYNC bit field
in its header matches the bit pattern in this field. The default is
0000b.
28
IRCVALL
Receive all
isochronous
packets
R/W
When the IRCVALL bit is set high, the TSB12LV32 receives all
isochronous packets regardless of the channel number or tag
number. The default is off.
29
–
30
RESERVED
Reserved
31
MONTAG
Match on tag
R/W
MONTAG is set when the user wants to only accept
isochronous packets that match both the tag field and the
channel number field. When set, MONTAG indicates that
isochronous receive data is accepted. The default is off.
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PDF描述 |
|---|---|
| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
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| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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