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參數資料
| 型號： | TSB12LV01B-EP |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 軍事增強塑料的高性能1394 3.3鏈路層電信。嵌入式 |
| 文件頁數： | 62/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01B-EP |
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5
–
6
Step 1:
Isochronous header quadlet is loaded into header0 register at 38h through a write
operation from the microcontroller interface.
Step 2:
Header quadlet is forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Isochronous packet is sent to the 1394 bus through the Phy.
NOTE:
The data coming through the data mover port is typically supplied by an external
fast memory block (i.e., FIFO, DRAM). This external memory logic may begin
transmitting data through to the data mover port exactly one DMCLK cycle after the
DMPRE output pin on the GP2Lynx is asserted high.
5.1.2.2
Isochronous Packet Transmit Without Automatic Header Insertion
In this mode, the packet header and data information is loaded through the data mover port. This mode is
sometimes called isochronous packet transmit with manual header insertion. This is because the header
quadlet is not preloaded into the header0 register via the microcontroller interface. Instead, it is inserted
manually
into the data stream at the same time as the rest of the packet. The following steps further illustrate
the process:
Step 1:
Isochronous header information (only one header quadlet in this case) is fetched into the
header0 register at 38h through the data mover port.
Step 2:
Header quadlet is forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Isochronous packet is sent to the 1394 bus through the Phy.
CFR REGISTER
Step 4
Data
Mover
Port
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Step 2
Step 3 (Packet Data)
Packet sent
to 1394 bus
through the
Phy
Step 1 (header fetched)
Step 1
(header supplied)
Step 3
(packet data)
Figure 5
–
8. Isochronous Transmit Without Auto Header Insertion
相關PDF資料 |
PDF描述 |
|---|---|
| TSB12LV01BPZ | FPGA (Field-Programmable Gate Array) |
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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