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參數資料
| 型號： | UJA1065 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High-speed CAN/LIN fail-safe system basis chip |
| 中文描述： | 高速的CAN / LIN故障防護系統基礎芯片 |
| 文件頁數： | 15/67頁 |
| 文件大小： | 285K |
| 代理商： | UJA1065 |
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9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
15 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
6.5 System reset
The reset function of the UJA1065 offers two signals to deal with reset events:
RSTN; the global ECU system reset
EN; a fail-safe global enable signal
6.5.1
RSTN pin
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW
with selectable pulse length upon the following events; see
Figure 3
:
Power-on (first battery connection) or BAT42 below Power-on reset threshold voltage
Low V1 supply
V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
V3 is down due to short-circuit condition during Sleep mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed
Successful exit from Flash mode
Wake-up from Standby mode via pins CAN, LIN or WAKE if programmed accordingly,
or any wake-up event from Sleep mode
Wake-up event from Fail-safe mode
Watchdog trigger failures (too early, overflow, wrong code)
Illegal mode code via SPI applied
Interrupt not served within t
RSTN(INT)
All of these reset events have a dedicated reset source in the System Status register to
allow distinction between the different events.
The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware
is properly reset. After the first battery connection, a short Power-on reset of 1 ms is
provided after voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit within the System Configuration Register; this allows the reset
pulse to be adjusted for future reset events. With this bit set, all reset events are
lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)
in Restart mode or with an externally applied falling edge at pin RSTN. With this
mechanism it is guaranteed that an erroneously shortened reset pulse will restart any
microcontroller, at least within the second trial by using the long reset pulse.
The behavior of pin RSTN is illustrated in
Figure 6
. The duration of t
RSTL
depends on the
setting of the RLC bit (defines the reset length). Once an external reset event is detected
the system controller enters the Start-up mode. The watchdog now starts to monitor pin
RSTN as illustrated in
Figure 7
. If the RSTN pin is not released in time then Fail-safe
mode is entered as shown in
Figure 3
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1065TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed CAN/LIN fail-safe system basis chip |
| UJA1065TW/3V0 | 功能描述:網絡控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0,512 | 功能描述:CAN 接口集成電路 HI SPEED CAN SYSTEM RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| UJA1065TW/3V0,518 | 功能描述:網絡控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
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