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| 型號： | UJA1065 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High-speed CAN/LIN fail-safe system basis chip |
| 中文描述： | 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片 |
| 文件頁數(shù)： | 37/67頁 |
| 文件大小： | 285K |
| 代理商： | UJA1065 |
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9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
37 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
6.13.8
System configuration register and system configuration feedback register
These registers allow configuration of the behavior of the SBC, and allow the settings to
be read back.
[1]
RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure
situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.
[2]
If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and LWS within the System Status register.
Table 11:
Bit
15 and 14
13
System configuration and system configuration feedback register bit description
Symbol
Description
Value
A1, A0
register address
10
RRS
Read Register Select
1
0
RO
Read Only
1
Function
select System Configuration register
read the General Purpose Feedback register 0
read the System Configuration Feedback register
read register selected by RRS without writing to System
Configuration register
read register selected by RRS and write to System
Configuration register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
V
th(GSD)(cm)
widened threshold
V
th(GSD)(cm)
normal threshold
t
RSTNL
long reset lengthening time selected
t
RSTNL
short reset lengthening time selected
Cyclic mode 2; t
w(CS)
long period; see
Figure 14
Cyclic mode 1; t
w(CS)
short period; see
Figure 14
continuously ON
OFF
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
an increasing V1 current causes a reset if the watchdog
was disabled during Standby mode
an increasing V1 current just reactivates the watchdog
during Standby mode, and an interrupt is forced (if enabled)
WAKE pin enabled
WAKE pin disabled
WAKE mode cyclic sample
WAKE mode continuous sample
INH/LIMP pin active (See ILC bit)
INH/LIMP pin floating
INH/LIMP pin HIGH if ILEN bit is set
INH/LIMP pin LOW if ILEN bit is set
12
0
11 and 10
-
reserved
0
9
GSTHC
GND Shift Threshold
Control
1
0
1
[1]
0
11
10
01
00
0
8
RLC
Reset Length Control
7 and 6
V3C[1:0]
V3 Control
5
-
reserved
4
V1CMC
V1 Current Monitor
Control
1
0
3
WEN
WAKE Enable
[2]
1
0
1
0
1
0
1
0
2
WSC
WAKE Sample Control
1
ILEN
INH/LIMP Enable
0
ILC
INH/LIMP Control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UJA1065TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed CAN/LIN fail-safe system basis chip |
| UJA1065TW/3V0 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0,512 | 功能描述:CAN 接口集成電路 HI SPEED CAN SYSTEM RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| UJA1065TW/3V0,518 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
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