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參數資料
| 型號： | UJA1065 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High-speed CAN/LIN fail-safe system basis chip |
| 中文描述： | 高速的CAN / LIN故障防護系統基礎芯片 |
| 文件頁數： | 21/67頁 |
| 文件大小： | 285K |
| 代理商： | UJA1065 |
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9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
21 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global
wake-up message is sufficient to wake-up the SBC. This pattern must be received within
t
timeout
after entering On-line Listen mode. Should t
timeout
elapse before receiving the
global wake-up message, then both messages are required for a CAN wake-up.
6.7.3
Termination control
In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated
to 0.5 x V
V2
via R
i
. In Off-line mode CANH and CANL are terminated to GND via R
i
. If V2
is disabled due to an overload condition both pins become floating.
6.7.4
Bus, RXD and TXD failure detection
The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in
Table 3
.
All failures are signalled separately in the CANFD bits in the System Diagnosis register.
Any change (detection and recovery) forces an interrupt to the microcontroller, if this
interrupt is enabled.
6.7.4.1
TXDC dominant clamping
If the TXDC pin is clamped dominant for longer than t
TXDC(dom)
the CAN transmitter is
disabled. After the TXDC pin becomes recessive the transmitter is re-activated
automatically when detecting bus activity or manually by setting and clearing the CTC bit.
Fig 9.
CAN wake-up timing diagram.
001aad446
CANH
CANL
wake-up
t
CAN(dom1)
t
CAN(reces)
t
CAN(dom2)
Table 3:
Failure
HxHIGH
HxGND
LxHIGH
LxGND
HxL
Bus dom
TXDC dom
RXDC reces
RXDC dom
CAN-bus, RXD and TXD failure detection
Description
CANH short-circuit to V
CC
, V
BAT14
or V
BAT42
CANH short-circuit to GND
CANL short-circuit to V
CC
, V
BAT14
or V
BAT42
CANL short-circuit to GND
CANH short-circuit to CANL
bus is continuously clamped dominant
pin TXDC is continuously clamped dominant
pin RXDC is continuously clamped recessive
pin RXDC is continuously clamped dominant
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UJA1065TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed CAN/LIN fail-safe system basis chip |
| UJA1065TW/3V0 | 功能描述:網絡控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0,512 | 功能描述:CAN 接口集成電路 HI SPEED CAN SYSTEM RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| UJA1065TW/3V0,518 | 功能描述:網絡控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
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