
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
54 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
[1]
V
V1(nom)
is 3 V, 3.3 V or 5 V, depending on the SBC version.
Not tested in production.
[2]
[3]
V2 internally supplies the SBC CAN transceiver. The performance of the CAN transceiver can be impaired if V2 is also used to supply
other circuitry while the CAN transceiver is in use.
9.
Dynamic characteristics
Temperature detection
T
j(warn)
high junction
temperature warning
level
160
175
190
°
C
Table 26:
T
vj
=
40
°
C to +150
°
C, V
BAT42
= 5.5 V to 52 V and V
BAT14
= 5.5 V to 27 V unless otherwise specified. All voltages are
defined with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction
temperature range by design. Products are 100 % tested at 125
°
C ambient temperature on wafer level (pre-testing). Cased
products are 100 % tested at 25
°
C ambient temperature (final testing). Both pre-testing and final testing use correlated test
conditions to cover the specified temperature and power supply voltage range.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
Table 27:
T
vj
=
40
°
C to + 150
°
C; V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; unless otherwise specified. All voltages are defined
with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature
range by design. Products are 100 % tested at 125
°
C ambient temperature on wafer level (pre-testing). Cased products are
100 % tested at 25
°
C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to
cover the specified temperature and power supply voltage range.
Symbol
Parameter
Conditions
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see
Figure 21
)
T
cyc
clock cycle time
t
lead
enable lead time
clock is low when SPI select
falls
t
lag
enable lag time
clock is low when SPI select
rises
t
SCKH
clock HIGH time
t
SCKL
clock LOW time
t
su
input data setup time
t
h
input data hold time
t
DOV
output data valid time pin SDO, C
L
= 10 pF
t
SSH
SPI select HIGH time
t
SSL
SPI select LOW time
CAN transceiver timing; pins CANL, CANH, TXDC and RXDC
t
t(reces-dom)
output transition time
recessive to dominant
R = 60
; see
Figure 17
and
Figure 18
t
t(dom-reces)
output transition time
dominant to recessive
R = 60
; see
Figure 17
and
Figure 18
t
PHL
propagation delay
TXDC to RXDC
(HIGH-to-LOW
transition)
Characteristics
Min
Typ
Max
Unit
480
240
-
-
-
-
ns
ns
240
-
-
ns
190
190
100
100
-
200
200
-
-
-
-
-
-
-
-
-
-
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
10 % to 90 %; C = 100 pF;
-
100
-
ns
90 % to 10 %; C = 100 pF;
-
100
-
ns
50 % V
TXDC
to 50 % V
RXDC
;
C = 100 pF; R = 60
; see
Figure 17
and
Figure 18
-
150
220
ns