
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
8 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Fig 3.
Main state diagram
001aad180
flash entry enabled (111/001/111 mode sequence)
OR mode change to Sleep with pending wake-up
OR watchdog not properly served
OR interrupt ignored
>
t
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
wake-up detected with its wake-up interrupt disabled
OR mode change to Sleep with pending wake-up
OR watchdog time-out with watchdog timeout interrupt disabled
OR watchdog OFF and I
>
I
thH(V1)
with reset option
OR interrupt ignored
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
Start-up mode
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
LIN: off-line
watchdog: start-up
INH/LIMP: HIGH/LOW/float
EN: LOW
Restart mode
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
LIN: off-line
watchdog: start-up
INH/LIMP: LOW/float
EN: LOW
Sleep mode
V1: OFF
SYSINH: HIGH/float
CAN: on-line/on-line listen/off-line
LIN: off-line
watchdog: time-out/OFF
INH/LIMP: LOW/float
RSTN: LOW
EN: LOW
Fail-safe mode
V1: OFF
SYSINH: HIGH/float
CAN: on-line/on-line listen/off-line
LIN: off-line
watchdog: OFF
INH/LIMP: LOW
RSTN: LOW
EN: LOW
Normal mode
V1: ON
SYSINH: HIGH
CAN: all modes available
LIN: all modes available
watchdog: window
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
Flash mode
V1: ON
SYSINH: HIGH
CAN: all modes available
LIN: all modes available
watchdog: time-out/OFF
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
Standby mode
V1: ON
SYSINH: HIGH
CAN: on-line/on-line listen/off-line
LIN: off-line
watchdog: time-out/OFF
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
mode change via SPI
mode change via SPI
mode change via SPI
Owake-up detected
OR V3 overload detected
wake-up detected
AND oscillator ok
AND t
t
ret
t
>
t
WD(init)
OR SPI clock count
16
OR RSTOR RSTN falling edge detected
OR illegal Mode register code
t
>
t
OR SPI clock count
16
OR RSTN falling edge detected
OR RSTNOR illegal Mode register code
leave Flash mode code
OR watchdog time-out
OR RSTN falling edge detected
>
t
RSTN(INT)
OR V1 undervoltage detected
OR illegal Mode register code
init Flash mode via SPI
init Normal mode
via SPI successful
init Normal mode
via SPI successful
supply connected
for the first time
from any
mode
oscillator fail
OR RSTN externally clamped HIGH detected
>
t
RSTN(CHT)
OR RSTN externally clamped LOW detected
>
t
RSTN(CLT)
OR RSTN released and V1 undervoltage detected
t
V1(CLT)
watchdog
trigger
watchdog
trigger
mode change via SPI
watchdog
trigger