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參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 16/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Rev. 0 | Page 16 of 92
H1 TO H8 PROGRAMMABLE EDGES:
1
H1 RISING EDGE.
2
H1 FALLING EDGE.
3
H5 RISING EDGE.
4
H5 FALLING EDGE.
Figure 17. HCLK Mode 3 Operation
H1, H3
H2, H4
H5, H7
H6, H8
1
2
3
4
0
P[0]
PIXEL
PERIOD
RG
HL
P[64] = P[0]
CCD
SIGNAL
P[32]
P[16]
P[48]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CONNECT H1, H3, H5, AND H7 TOGETHER AND H2, H4, H6, AND H8 TOGETHER FOR MAXIMUM DRIVE STRENGTH.
Figure 18. High Speed Timing Default Locations
POSITION
H2, H4, H6, H8
RGr[0]
RGf[16]
HLr[0]
HLf[32]
H1, H3, H5, H7
H1r[0]
H1f[32]
SHP[32]
t
S1
SHD[0]
0
Digital Data Outputs
The AD9992 data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x38, Bits [11:0]).
DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to
63, as shown in Figure 19. DOUTPHASEN (Bits [11:6]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).
Normally, the DOUT and DCLK signals track in phase, based
on the contents of the DOUTPHASE registers. The DCLK output
phase can also be held fixed with respect to the data outputs by
changing the DCLKMODE register high (Address 0x38, Bit [12]).
In this mode, the DCLK output remains at a fixed phase equal
to a delayed version of CLI while the data output phase is still
programmable.
The pipeline delay through the AD9992 is shown in Figure 20.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
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