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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 76/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
COMPLETE REGISTER LISTING
When an address contains less than 28 data bits, all remaining bits must be written as 0s.
Table 28. AFE Registers
Data
Bits
Value
Type
00
[1:0]
3
SCK
Rev. 0 | Page 76 of 92
Address
Default
Update
Name
STANDBY
Description
Standby modes. 0: normal operation; 1: Standby1 mode;
2: Standby2 mode; 3: Standby3 mode.
0: disable OB clamp; 1: enable OB clamp.
0: select normal OB clamp settling; 1: select fast OB clamp settling.
0: ignore CDS gain; 1: very fast clamping when CDS gain is updated.
0: blank data outputs to 0 during PBLK;
1: blank data outputs to programmed clamp level during PBLK.
0: enable input dc restore circuit during PBLK;
1: disable input dc restore circuit during PBLK.
0: data outputs are driven; 1: data outputs are three-stated.
0: latch data outputs using the rising edge of DOUTPHASEP
(DOUTPHASEP register setting);
1: output latch is transparent.
1: enable gray encoding of the digital data outputs.
Set to 0.
Do not access, or set to 0.
Do not access, or set to 0xFFFFFF.
CDS gain setting. 0: 3 dB; 4: 0 dB; 6: +3 dB; 7: +6 dB.
All other values are invalid.
VGA gain, 6 dB to 42 dB (0.035 dB per step).
Optical black clamp level, 0 to 1023 LSB (1 LSB per step).
0: no division of CLI; 1: divide CLI input frequency by 2.
[2]
[3]
[4]
[5]
1
0
0
0
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
[6]
0
DCBYP
01
[0]
[1]
0
0
SCK
DOUTDISABLE
DOUTLATCH
02
03
04
[2]
[3]
[0]
[23:0]
[2:0]
0
1
0
FFFFFF
0
SCK
SCK
VD
GRAY_EN
TEST
TEST
TEST
CDSGAIN
05
06
0D
[9:0]
[9:0]
[0]
F
1EC
0
VD
VD
VD
VGAGAIN
CLAMPLEVEL
CLIDIVIDE
Table 29. Miscellaneous Registers
Data
Bits
10
[0]
Address
Default
Value
0
Update
Type
SCK
Name
SW_RST
Description
Software reset. Bit self-clears to 0 when a reset occurs.
1: reset Address 0x00 to Address 0xFF to default values.
0: make all outputs dc inactive; 1: enable outputs at next VD
edge.
1: configure SYNC pin as RSTB input signal.
Test mode only. Must be set to 0.
1: external synchronization enable (configures Pin D3 as an
input).
SYNC active polarity.
Suspend clocks during SYNC active pulse. 0: don’t suspend;
1: suspend.
1: enable enhanced sync/shutter operations.
1: mask HD during SYNCSUSPEND.
1: mask VD during SYNCSUSPEND.
1: mask XV outputs during SYNCSUSPEND.
1: enable use of shadow registers.
Test mode only. Must be set to 0.
1: writes to shadow bits affect shadow registers, not primary.
1: initiate software SYNC event (self-clears to 0 after SYNC).
Timing core reset bar. 0: reset TG core; 1: resume operation.
11
[0]
0
VD
OUTCONTROL
12
13
[0]
[4:1]
[0]
0
0
1
SCK
SCK
RSTB_EN
TEST
SYNCENABLE
[1]
[2]
0
0
SYNCPOL
SYNCSUSPEND
14
[3]
[4]
[5]
[6]
[7]
[12:8]
[13]
[14]
[0]
0
0
1
1
0
0
0
0
0
SCK
ENH_SYNC_EN
SYNC_MASK_HD
SYNC_MASK_VD
SYNC_MASK_V
SHADOW_EN
TEST
UPDATE_SHADOW
SWSYNC
TGCORE_RSTB
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
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